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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 8si1570390yba.109.2017.11.03.11.56.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 03 Nov 2017 11:56:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@braap.org header.s=mesmtp header.b=mUkV63D3; dkim=fail header.i=@messagingengine.com header.s=fm1 header.b=XXDlc7m2; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Received: from localhost ([::1]:38073 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAh8i-0003s8-Mi for alex.bennee@linaro.org; Fri, 03 Nov 2017 14:56:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAh8a-0003qh-IL for qemu-arm@nongnu.org; Fri, 03 Nov 2017 14:56:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eAh8V-0005X1-OA for qemu-arm@nongnu.org; Fri, 03 Nov 2017 14:56:16 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:56567) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eAh8V-0005WS-I7; Fri, 03 Nov 2017 14:56:11 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id EF2F220AC5; Fri, 3 Nov 2017 14:56:10 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Fri, 03 Nov 2017 14:56:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= mesmtp; bh=Ti16a4mXjd5BYWl5Dtllj1w4u+V1/hpw7YWsIjkyEwo=; b=mUkV6 3D3YTLD/LWdL4DMntPUZ4KcUiCzhqHhD7Le0bzxn4KgHU/hHM4L5ujPKSkTWibIo gJxJj3cuxCqaOae6NhG4z15qgYv+zorXFSJOQyU/QaB71rp00qXf95Fh4sHU+BuO vO78PT/dhOevOhGV7g6VfrTtox13KdD2jwWW+4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=Ti16a4mXjd5BYWl5Dtllj1w4u+V1/ hpw7YWsIjkyEwo=; b=XXDlc7m2riBmviX7Q9nqyRIDkXnNdXzlNoLnz48Z3BZZP pi33ppC33WaBWaNRABr8MJ2bkPyUwyrh3I0ps60riNdsHq//gYieJ6GchKIdaZq8 uU3UnO7xHFbEI9feRFo456Yk3O5zbL9GqGTZE63lhriIEh1mCPARRMsJqSv1ytzJ uC86Zj8OgDFUdN26MgP9LtiloCxOfeeUwl/+mtEOcuExwEu8MyvEKPXwWFMO3ymE FFe1AzG9tAXrgFte3Bo8h2dnpPr2AaDWSB4TYDmKgqLe/sblc5IYrMd0Og4jfrwz EsCllG8J20Ijx2TOHaJ6diTnIY5R07Un8+JkNylrg== X-ME-Sender: Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id BE7902489B; Fri, 3 Nov 2017 14:56:10 -0400 (EDT) Date: Fri, 3 Nov 2017 14:56:10 -0400 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Message-ID: <20171103185610.GA3907@flamenco> References: <1509734853-3014-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1509734853-3014-1-git-send-email-cota@braap.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 Subject: Re: [Qemu-arm] [PATCH] hw: add .min_cpus and .default_cpus fields to machine_class X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Eduardo Habkost , Igor Mitsyanko , Richard Henderson , Alistair Francis , qemu-arm@nongnu.org, Marcel Apfelbaum Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: Yofz2ToKEhdj On Fri, Nov 03, 2017 at 14:47:33 -0400, Emilio G. Cota wrote: > diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c > index e2d15a1..395d1b5 100644 > --- a/hw/arm/xlnx-zcu102.c > +++ b/hw/arm/xlnx-zcu102.c > @@ -185,6 +185,9 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > mc->ignore_memory_transaction_failures = true; > + mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; > + mc->min_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > } > > static const TypeInfo xlnx_ep108_machine_init_typeinfo = { > @@ -241,6 +244,8 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) > mc->units_per_default_bus = 1; > mc->ignore_memory_transaction_failures = true; > mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; > + mc->min_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > } Should we update max_cpus to just NUM_APU_CPUS as well for these boards? -smp 5 or 6 (NUM_APU + NUM_RPU) still gets us 4 vCPUs. I see there's code for RPU cpus but it seems disabled at compile-time at xlnx-zynqmp.c:431: DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false) Or is there a run-time way to override this? Thanks, Emilio From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59856) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAh8c-0003s7-GS for qemu-devel@nongnu.org; Fri, 03 Nov 2017 14:56:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eAh8b-0005dm-MI for qemu-devel@nongnu.org; Fri, 03 Nov 2017 14:56:18 -0400 Date: Fri, 3 Nov 2017 14:56:10 -0400 From: "Emilio G. Cota" Message-ID: <20171103185610.GA3907@flamenco> References: <1509734853-3014-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1509734853-3014-1-git-send-email-cota@braap.org> Subject: Re: [Qemu-devel] [PATCH] hw: add .min_cpus and .default_cpus fields to machine_class List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Thomas Huth , qemu-arm@nongnu.org, Igor Mitsyanko , Alistair Francis , "Edgar E . Iglesias" , Eduardo Habkost , Marcel Apfelbaum On Fri, Nov 03, 2017 at 14:47:33 -0400, Emilio G. Cota wrote: > diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c > index e2d15a1..395d1b5 100644 > --- a/hw/arm/xlnx-zcu102.c > +++ b/hw/arm/xlnx-zcu102.c > @@ -185,6 +185,9 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) > mc->block_default_type = IF_IDE; > mc->units_per_default_bus = 1; > mc->ignore_memory_transaction_failures = true; > + mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; > + mc->min_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > } > > static const TypeInfo xlnx_ep108_machine_init_typeinfo = { > @@ -241,6 +244,8 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) > mc->units_per_default_bus = 1; > mc->ignore_memory_transaction_failures = true; > mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; > + mc->min_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; > } Should we update max_cpus to just NUM_APU_CPUS as well for these boards? -smp 5 or 6 (NUM_APU + NUM_RPU) still gets us 4 vCPUs. I see there's code for RPU cpus but it seems disabled at compile-time at xlnx-zynqmp.c:431: DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false) Or is there a run-time way to override this? Thanks, Emilio