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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Read ilk FDI PLL frequency once during initialisation
Date: Tue, 7 Nov 2017 23:25:44 +0200	[thread overview]
Message-ID: <20171107212544.GT10981@intel.com> (raw)
In-Reply-To: <20171105134905.4636-1-chris@chris-wilson.co.uk>

On Sun, Nov 05, 2017 at 01:49:05PM +0000, Chris Wilson wrote:
> During intel_atomic_check(), we do not take the intel_runtime_pm_get()
> wakeref and so should do the atomic modeset precalculations without
> referring to the HW. However, on Ironlake we see
> 
> <7>[   23.487557] [drm:intel_atomic_check [i915]] [CONNECTOR:47:VGA-1] checking for sink bpp constrains
> <7>[   23.487615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
> <4>[   23.487621] RPM wakelock ref not held during HW access
> <4>[   23.487652] ------------[ cut here ]------------
> <4>[   23.487697] WARNING: CPU: 0 PID: 1343 at drivers/gpu/drm/i915/intel_drv.h:1813 gen5_read32+0x183/0x200 [i915]
> <4>[   23.487701] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm lpc_ich e1000e mei_me ptp mei pps_core prime_numbers
> <4>[   23.487784] CPU: 0 PID: 1343 Comm: debugfs_test Tainted: G        W       4.14.0-rc7-CI-Trybot_1378+ #1
> <4>[   23.487788] Hardware name: Hewlett-Packard HP Compaq 8100 Elite SFF PC/304Ah, BIOS 786H1 v01.13 07/14/2011
> <4>[   23.487793] task: ffff8801f90aa6c0 task.stack: ffffc900013ec000
> <4>[   23.487838] RIP: 0010:gen5_read32+0x183/0x200 [i915]
> <4>[   23.487842] RSP: 0018:ffffc900013efb58 EFLAGS: 00010292
> <4>[   23.487849] RAX: 000000000000002a RBX: ffff880205c00000 RCX: 0000000000000006
> <4>[   23.487854] RDX: 000000000000140a RSI: ffffffff81d0eb14 RDI: ffffffff81cc26f6
> <4>[   23.487857] RBP: ffffc900013efb80 R08: ffff8801f90aaff8 R09: 0000000000000000
> <4>[   23.487861] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000001
> <4>[   23.487865] R13: 0000000000046000 R14: ffff88020ffaba78 R15: ffff88020b109bf8
> <4>[   23.487870] FS:  00007f53b5e40a40(0000) GS:ffff88021bc00000(0000) knlGS:0000000000000000
> <4>[   23.487874] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[   23.487878] CR2: 000055e41900c0e8 CR3: 00000001fa0d6005 CR4: 00000000000206f0
> <4>[   23.487882] Call Trace:
> <4>[   23.487931]  intel_atomic_check+0x745/0x1290 [i915]
> <4>[   23.487948]  drm_atomic_check_only+0x459/0x560
> <4>[   23.487956]  ? drm_atomic_set_crtc_for_connector+0xc9/0x100
> <4>[   23.488025]  drm_atomic_commit+0x18/0x50
> <4>[   23.488035]  restore_fbdev_mode_atomic+0x190/0x1f0
> <4>[   23.488059]  restore_fbdev_mode+0x32/0x120
> <4>[   23.488072]  drm_fb_helper_restore_fbdev_mode_unlocked+0x50/0xa0
> <4>[   23.488139]  intel_fbdev_restore_mode+0x34/0x90 [i915]
> <4>[   23.488194]  i915_driver_lastclose+0xe/0x10 [i915]
> <4>[   23.488208]  drm_lastclose+0x39/0xf0
> <4>[   23.488219]  drm_release+0x30c/0x3c0
> <4>[   23.488236]  __fput+0xb9/0x200
> <4>[   23.488252]  ____fput+0xe/0x10
> <4>[   23.488264]  task_work_run+0x89/0xc0
> <4>[   23.488278]  exit_to_usermode_loop+0x83/0x90
> <4>[   23.488290]  syscall_return_slowpath+0xd0/0x110
> <4>[   23.488304]  entry_SYSCALL_64_fastpath+0xaf/0xb1
> <4>[   23.488312] RIP: 0033:0x7f53b4317560
> <4>[   23.488320] RSP: 002b:00007ffca7e70748 EFLAGS: 00000246 ORIG_RAX: 0000000000000003
> <4>[   23.488333] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 00007f53b4317560
> <4>[   23.488340] RDX: 0000000000000005 RSI: 00007ffca7e70640 RDI: 0000000000000004
> <4>[   23.488347] RBP: 000055e417783900 R08: 000055e418f9e290 R09: 0000000000000000
> <4>[   23.488356] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000001
> <4>[   23.488363] R13: 00007f53b4302c40 R14: 0000000000000000 R15: 0000000000000000
> <4>[   23.488384] Code: b5 f2 f2 e0 0f ff e9 c5 fe ff ff 80 3d 0e 4b 10 00 00 0f 85 c6 fe ff ff 48 c7 c7 30 73 29 a0 c6 05 fa 4a 10 00 01 e8 8e f2 f2 e0 <0f> ff e9 ac fe ff ff e8 51 9d f3 e0 85 c0 0f 85 01 ff ff ff 48
> <4>[   23.488780] ---[ end trace 6bc72ce7f1596190 ]---
> <7>[   23.488844] [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 1
> <7>[   23.488911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
> 
> due to intel_fdi_link_freq() poking at FDI_PLL_BIOS_0. Avoid this by
> recording the fdi pll frequency during device initiailisation.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 1 +
>  drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72bb5b51035a..ed58eaf7b082 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2344,6 +2344,7 @@ struct drm_i915_private {
>  	unsigned int max_dotclk_freq;
>  	unsigned int rawclk_freq;
>  	unsigned int hpll_freq;
> +	unsigned int fdi_pll_freq;
>  	unsigned int czclk_freq;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 737de251d0f8..768a4e75e535 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -220,7 +220,7 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv,
>  	if (HAS_DDI(dev_priv))
>  		return pipe_config->port_clock; /* SPLL */
>  	else if (IS_GEN5(dev_priv))
> -		return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
> +		return dev_priv->fdi_pll_freq;
>  	else
>  		return 270000;
>  }
> @@ -14542,6 +14542,11 @@ int intel_modeset_init(struct drm_device *dev)
>  
>  	intel_shared_dpll_init(dev);
>  
> +	if (IS_GEN5(dev_priv)) {
> +		dev_priv->fdi_pll_freq = ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
> +		DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
> +	}

else if (SNB || IVB)
	->fdi_pll_freq = 270000; ?

and maybe extract the whole mess into intel_update_fdi_pll_freq() or some such
thing?

> +
>  	intel_update_czclk(dev_priv);
>  	intel_modeset_init_hw(dev);
>  
> -- 
> 2.15.0

-- 
Ville Syrjälä
Intel OTC
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  parent reply	other threads:[~2017-11-07 21:25 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-05 13:49 [PATCH] drm/i915: Read ilk FDI PLL frequency once during initialisation Chris Wilson
2017-11-05 14:36 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-05 15:23 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-07 21:25 ` Ville Syrjälä [this message]
2017-11-07 21:47 ` [PATCH v2] " Chris Wilson
2017-11-08  7:47   ` Maarten Lankhorst
2017-11-08  9:24     ` Chris Wilson
2017-11-08 11:22   ` Ville Syrjälä
2017-11-08 15:48     ` Chris Wilson
2017-11-08  9:48 ` ✓ Fi.CI.BAT: success for drm/i915: Read ilk FDI PLL frequency once during initialisation (rev2) Patchwork
2017-11-08 10:50 ` ✓ Fi.CI.IGT: " Patchwork

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