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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id k10si1160567ywa.703.2017.11.08.13.52.34 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 08 Nov 2017 13:52:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:34050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCYGw-0003x1-CE for alex.bennee@linaro.org; Wed, 08 Nov 2017 16:52:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45245) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCYGl-0003wh-8r for qemu-arm@nongnu.org; Wed, 08 Nov 2017 16:52:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCYGh-00079b-Cc for qemu-arm@nongnu.org; Wed, 08 Nov 2017 16:52:23 -0500 Received: from mx1.redhat.com ([209.132.183.28]:51048) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eCYGh-000799-6S; Wed, 08 Nov 2017 16:52:19 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 389A2C0587F4; Wed, 8 Nov 2017 21:52:17 +0000 (UTC) Received: from localhost (ovpn-116-35.gru2.redhat.com [10.97.116.35]) by smtp.corp.redhat.com (Postfix) with ESMTP id 19E6E5EDF5; Wed, 8 Nov 2017 21:52:13 +0000 (UTC) Date: Wed, 8 Nov 2017 19:52:12 -0200 From: Eduardo Habkost To: Richard Henderson Message-ID: <20171108215212.GW3111@localhost.localdomain> References: <1509734853-3014-1-git-send-email-cota@braap.org> <20171103185610.GA3907@flamenco> <20171103200233.GI3111@localhost.localdomain> <20171103222407.GA22411@flamenco> <20171106141022.GO3111@localhost.localdomain> <20171106201332.GA2152@flamenco> <73e9c472-82da-b293-27cd-ca9e0ff93179@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <73e9c472-82da-b293-27cd-ca9e0ff93179@linaro.org> X-Fnord: you can see the fnord User-Agent: Mutt/1.9.1 (2017-09-22) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 08 Nov 2017 21:52:17 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw: add .min_cpus and .default_cpus fields to machine_class X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Igor Mitsyanko , qemu-devel@nongnu.org, Alistair Francis , "Emilio G. Cota" , qemu-arm@nongnu.org, Igor Mammedov , Marcel Apfelbaum Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: 6BjdrTgzcGqe On Wed, Nov 08, 2017 at 10:29:43PM +0100, Richard Henderson wrote: > On 11/06/2017 09:13 PM, Emilio G. Cota wrote: > > Subject: [PATCH] qom: move CPUClass.tcg_initialize to a global > > > > 55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24) > > introduces a per-CPUClass bool that we check so that the target CPU > > is initialized for TCG only once. This works well except when > > we end up creating more than one CPUClass, in which case we end > > up incorrectly initializing TCG more than once, i.e. once for > > each CPUClass. > > > > This can be replicated with: > > $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \ > > -global driver=xlnx,,zynqmp,property=has_rpu,value=on > > In this case the class name of the "RPUs" is prefixed by "cortex-r5-", > > whereas the "regular" CPUs are prefixed by "cortex-a53-". This > > results in two CPUClass instances being created. > > > > Fix it by introducing a static variable, so that only the first > > target CPU being initialized will initialize the target-dependent > > part of TCG, regardless of CPUClass instances. > > Hah! > > So, I had been thinking of the xylinx ARM + Microblaze case, where we really do > need two different initializations. I never imagined that two different ARM > parts had different CPUClasses. Is xylinx ARM + Microblaze something that already works (and would be broken by this patch), or something planned for the future? > > So I guess it's my initial patch that unified this that's more buggy than not. We still have the option of reverting the original patch, but (if it doesn't break anything) this patch looks like a simpler fix for 2.11 than a full revert. -- Eduardo From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCYGn-0003x2-7b for qemu-devel@nongnu.org; Wed, 08 Nov 2017 16:52:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCYGm-0007AZ-DQ for qemu-devel@nongnu.org; Wed, 08 Nov 2017 16:52:25 -0500 Date: Wed, 8 Nov 2017 19:52:12 -0200 From: Eduardo Habkost Message-ID: <20171108215212.GW3111@localhost.localdomain> References: <1509734853-3014-1-git-send-email-cota@braap.org> <20171103185610.GA3907@flamenco> <20171103200233.GI3111@localhost.localdomain> <20171103222407.GA22411@flamenco> <20171106141022.GO3111@localhost.localdomain> <20171106201332.GA2152@flamenco> <73e9c472-82da-b293-27cd-ca9e0ff93179@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <73e9c472-82da-b293-27cd-ca9e0ff93179@linaro.org> Subject: Re: [Qemu-devel] [PATCH] hw: add .min_cpus and .default_cpus fields to machine_class List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: "Emilio G. Cota" , qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , qemu-arm@nongnu.org, Igor Mitsyanko , Alistair Francis , "Edgar E . Iglesias" , Marcel Apfelbaum , Igor Mammedov On Wed, Nov 08, 2017 at 10:29:43PM +0100, Richard Henderson wrote: > On 11/06/2017 09:13 PM, Emilio G. Cota wrote: > > Subject: [PATCH] qom: move CPUClass.tcg_initialize to a global > > > > 55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24) > > introduces a per-CPUClass bool that we check so that the target CPU > > is initialized for TCG only once. This works well except when > > we end up creating more than one CPUClass, in which case we end > > up incorrectly initializing TCG more than once, i.e. once for > > each CPUClass. > > > > This can be replicated with: > > $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \ > > -global driver=xlnx,,zynqmp,property=has_rpu,value=on > > In this case the class name of the "RPUs" is prefixed by "cortex-r5-", > > whereas the "regular" CPUs are prefixed by "cortex-a53-". This > > results in two CPUClass instances being created. > > > > Fix it by introducing a static variable, so that only the first > > target CPU being initialized will initialize the target-dependent > > part of TCG, regardless of CPUClass instances. > > Hah! > > So, I had been thinking of the xylinx ARM + Microblaze case, where we really do > need two different initializations. I never imagined that two different ARM > parts had different CPUClasses. Is xylinx ARM + Microblaze something that already works (and would be broken by this patch), or something planned for the future? > > So I guess it's my initial patch that unified this that's more buggy than not. We still have the option of reverting the original patch, but (if it doesn't break anything) this patch looks like a simpler fix for 2.11 than a full revert. -- Eduardo