Re: [PATCH v2 1/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

[Zhong Yang <yang.zhong@intel.com>]

On Fri, Nov 10, 2017 at 03:32:45AM -0700, Jan Beulich wrote:
> >>> On 10.11.17 at 10:36, <yang.zhong@intel.com> wrote:
> > Intel IceLake cpu has added new cpu features: AVX512VBMI2/GFNI/
> > VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
> > need expose to guest.
> > 
> > The bit definition:
> > CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
> > CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
> > CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
> > CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> > CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
> > CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> > 
> > The release document ref below link:
> > https://software.intel.com/sites/default/files/managed/c5/15/\ 
> > architecture-instruction-set-extensions-programming-reference.pdf
> > 
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> 
> Properly placed last in the series, the non-toolstack parts here
> Acked-by: Jan Beulich <jbeulich@suse.com>
> 
> Jan

  Hello Jan,

  Thanks for reviewing my patch!

  I adjusted the patches sequence and sent V3 to Xen community, please
  help review new patches series, many thanks!

  Regards,

  Yang 

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