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From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [RFC 4/5] drm/i915: Re-arrange execbuf so context is known before engine
Date: Mon, 13 Nov 2017 13:09:08 +0000	[thread overview]
Message-ID: <20171113130909.31345-5-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20171113130909.31345-1-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Needed for a following patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 38 ++++++++++++++++--------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f7aabea601b0..ecb6290ab6ee 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2258,24 +2258,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	if (args->flags & I915_EXEC_IS_PINNED)
 		eb.batch_flags |= I915_DISPATCH_PINNED;
 
-	eb.engine = eb_select_engine(eb.i915, file, args);
-	if (!eb.engine)
-		return -EINVAL;
-
-	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
-		if (!HAS_RESOURCE_STREAMER(eb.i915)) {
-			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
-			return -EINVAL;
-		}
-		if (eb.engine->id != RCS) {
-			DRM_DEBUG("RS is not available on %s\n",
-				 eb.engine->name);
-			return -EINVAL;
-		}
-
-		eb.batch_flags |= I915_DISPATCH_RS;
-	}
-
 	if (args->flags & I915_EXEC_FENCE_IN) {
 		in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
 		if (!in_fence)
@@ -2300,6 +2282,25 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	if (unlikely(err))
 		goto err_destroy;
 
+	err = -EINVAL;
+	eb.engine = eb_select_engine(eb.i915, file, args);
+	if (!eb.engine)
+		goto err_engine;
+
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!HAS_RESOURCE_STREAMER(eb.i915)) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
+			goto err_engine;
+		}
+		if (eb.engine->id != RCS) {
+			DRM_DEBUG("RS is not available on %s\n",
+				  eb.engine->name);
+			goto err_engine;
+		}
+
+		eb.batch_flags |= I915_DISPATCH_RS;
+	}
+
 	/*
 	 * Take a local wakeref for preparing to dispatch the execbuf as
 	 * we expect to access the hardware fairly frequently in the
@@ -2460,6 +2461,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	mutex_unlock(&dev->struct_mutex);
 err_rpm:
 	intel_runtime_pm_put(eb.i915);
+err_engine:
 	i915_gem_context_put(eb.ctx);
 err_destroy:
 	eb_destroy(&eb);
-- 
2.14.1

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  parent reply	other threads:[~2017-11-13 13:09 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-13 13:09 [RFC 0/5] Class/instance based execbuf plus more Tvrtko Ursulin
2017-11-13 13:09 ` [RFC 1/5] drm/i915: Select engines via class and instance in execbuffer2 Tvrtko Ursulin
2017-11-13 13:09 ` [RFC 2/5] drm/i915: Engine capabilities uAPI Tvrtko Ursulin
2017-11-13 13:13   ` Chris Wilson
2017-11-13 13:17   ` Chris Wilson
2017-11-13 13:09 ` [RFC 3/5] drm/i915: Concurrent context uAPI Tvrtko Ursulin
2017-11-13 13:19   ` Chris Wilson
2017-11-13 13:23     ` Chris Wilson
2017-11-13 13:28   ` Chris Wilson
2017-11-13 13:09 ` Tvrtko Ursulin [this message]
2017-11-13 13:09 ` [RFC 5/5] drm/i915: Per batch buffer VCS balancing Tvrtko Ursulin
2017-11-16  0:21   ` Oscar Mateo
2017-11-16  9:57     ` Chris Wilson
2017-11-13 13:13 ` ✗ Fi.CI.BAT: failure for Class/instance based execbuf plus more Patchwork

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