Re: [PATCH rdma-core 1/2] verbs: Report the device's PCI write end paddding capability

[Jason Gunthorpe <jgg-uk2M96/98Pc@public.gmane.org>]

On Tue, Nov 14, 2017 at 03:47:07PM +0200, Yishai Hadas wrote:
> From: Noa Osherovich <noaos-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
> 
> There are PCIe root complex that are able to optimize their
> performance when incoming data is multiple full cache lines.
> Expose the device capability to report whether the device supports
> padding the ending of incoming packets to full cache line, such that
> the last upstream write generated by the incoming packet will be a
> full cache line.
> 
> User should consider several factors before activating this feature:
> - In case of high CPU memory load (which may cause PCI backpressure in
>   turn), if a large percent of the writes are partial cache line, this
>   feature should be checked as an optional solution.
> - This feature might reduce performance if most packets are between
>   one and two cache lines and PCIe throughput has reached its maximum
>   capacity. E.g. 65B packet from the network port will lead to 128B
>   write on PCIe, which may cause trafiic on PCIe to reach high
>   throughput.

This commit message would make a far better man page revision than
what was provided :(

Jason
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