diff for duplicates of <20171114234643.GD11955@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 50ee286..7d8eb01 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ On 11/14, Alexey Brodkin wrote: > Hi Vladimir, > -> On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote: +> On Tue, 2017-11-14@19:01 +0200, Vladimir Zapolskiy wrote: > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote: > > > > > > Add option to set initial output frequency of plls via @@ -14,56 +14,56 @@ On 11/14, Alexey Brodkin wrote: > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW > > > chYfhSGT2M&e= > > > -> > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> +> > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> > > > --- -> > > .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ -> > > .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ -> > > drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- -> > > drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- -> > > 4 files changed, 74 insertions(+), 4 deletions(-) +> > > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++ +> > > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++ +> > > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++-- +> > > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++-- +> > > ?4 files changed, 74 insertions(+), 4 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > index c56c755..5703059 100644 > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > @@ -13,6 +13,10 @@ Required properties: -> > > - clocks: shall be the input parent clock phandle for the PLL. -> > > - #clock-cells: from common clock binding; Should always be set to 0. -> > > +> > > ?- clocks: shall be the input parent clock phandle for the PLL. +> > > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > > ? > > > +Optional properties: > > > +- clock-frequency: output frequency generated by pll in Hz which will be set > > > +while probing. Should be a single cell. > > > + -> > > Example: -> > > input_clk: input-clk { -> > > clock-frequency = <33333333>; +> > > ?Example: +> > > ? input_clk: input-clk { +> > > ? clock-frequency = <33333333>; > > > @@ -25,4 +29,5 @@ Example: -> > > reg = <0x00 0x10>; -> > > #clock-cells = <0>; -> > > clocks = <&input_clk>; +> > > ? reg = <0x00 0x10>; +> > > ? #clock-cells = <0>; +> > > ? clocks = <&input_clk>; > > > + clock-frequency = <1000000000>; -> > > }; +> > > ? }; > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > index 11fe487..5908f99 100644 > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. -> > > - clocks: shall be the input parent clock phandle for the PLL. -> > > - #clock-cells: from common clock binding; Should always be set to 0. -> > > +> > > ?- clocks: shall be the input parent clock phandle for the PLL. +> > > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > > ? > > > +Optional properties: > > > +- clock-frequency: output frequency generated by pll in Hz which will be set > > > +while probing. Should be a single cell. > > > + -> > > Example: -> > > input-clk: input-clk { -> > > clock-frequency = <33333333>; +> > > ?Example: +> > > ? input-clk: input-clk { +> > > ? clock-frequency = <33333333>; > > > @@ -25,4 +29,5 @@ Example: -> > > reg = <0x80 0x10>, <0x100 0x10>; -> > > #clock-cells = <0>; -> > > clocks = <&input-clk>; +> > > ? reg = <0x80 0x10>, <0x100 0x10>; +> > > ? #clock-cells = <0>; +> > > ? clocks = <&input-clk>; > > > + clock-frequency = <100000000>; -> > > }; +> > > ? }; > > > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt > > about how to assign initial clock rates, in general 'clock-frequency' diff --git a/a/content_digest b/N1/content_digest index 068ed59..2d90157 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,16 @@ "ref\020171114122020.9800-1-Eugeniy.Paltsev@synopsys.com\0" "ref\01b07abf9-c94d-1759-4182-519b77c8bb37@mentor.com\0" "ref\01510694373.15407.1.camel@synopsys.com\0" - "From\0sboyd@codeaurora.org <sboyd@codeaurora.org>\0" - "Subject\0Re: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" + "From\0sboyd@codeaurora.org (sboyd@codeaurora.org)\0" + "Subject\0[PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" "Date\0Tue, 14 Nov 2017 15:46:43 -0800\0" - "To\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" - "Cc\0vladimir_zapolskiy@mentor.com <vladimir_zapolskiy@mentor.com>" - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - robh+dt@kernel.org <robh+dt@kernel.org> - mturquette@baylibre.com <mturquette@baylibre.com> - Eugeniy.Paltsev@synopsys.com <Eugeniy.Paltsev@synopsys.com> - linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org> - mark.rutland@arm.com <mark.rutland@arm.com> - " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" "On 11/14, Alexey Brodkin wrote:\n" "> Hi Vladimir,\n" "> \n" - "> On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:\n" + "> On Tue, 2017-11-14@19:01 +0200, Vladimir Zapolskiy wrote:\n" "> > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:\n" "> > > \n" "> > > Add option to set initial output frequency of plls via\n" @@ -31,56 +23,56 @@ "> > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW\n" "> > > chYfhSGT2M&e=\n" "> > > \n" - "> > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" + "> > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" "> > > ---\n" - "> > > \302\240.../bindings/clock/snps,hsdk-pll-clock.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++\n" - "> > > \302\240.../devicetree/bindings/clock/snps,pll-clock.txt\302\240\302\240\302\240|\302\240\302\2405 ++++\n" - "> > > \302\240drivers/clk/axs10x/pll_clock.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" - "> > > \302\240drivers/clk/clk-hsdk-pll.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" - "> > > \302\2404 files changed, 74 insertions(+), 4 deletions(-)\n" + "> > > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++\n" + "> > > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++\n" + "> > > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++--\n" + "> > > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++--\n" + "> > > ?4 files changed, 74 insertions(+), 4 deletions(-)\n" "> > > \n" "> > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" "> > > index c56c755..5703059 100644\n" "> > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" "> > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" "> > > @@ -13,6 +13,10 @@ Required properties:\n" - "> > > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" - "> > > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" - "> > > \302\240\n" + "> > > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > ?\n" "> > > +Optional properties:\n" "> > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" "> > > +while probing. Should be a single cell.\n" "> > > +\n" - "> > > \302\240Example:\n" - "> > > \302\240\tinput_clk: input-clk {\n" - "> > > \302\240\t\tclock-frequency = <33333333>;\n" + "> > > ?Example:\n" + "> > > ?\tinput_clk: input-clk {\n" + "> > > ?\t\tclock-frequency = <33333333>;\n" "> > > @@ -25,4 +29,5 @@ Example:\n" - "> > > \302\240\t\treg = <0x00 0x10>;\n" - "> > > \302\240\t\t#clock-cells = <0>;\n" - "> > > \302\240\t\tclocks = <&input_clk>;\n" + "> > > ?\t\treg = <0x00 0x10>;\n" + "> > > ?\t\t#clock-cells = <0>;\n" + "> > > ?\t\tclocks = <&input_clk>;\n" "> > > +\t\tclock-frequency = <1000000000>;\n" - "> > > \302\240\t};\n" + "> > > ?\t};\n" "> > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" "> > > index 11fe487..5908f99 100644\n" "> > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" "> > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" "> > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" - "> > > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" - "> > > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" - "> > > \302\240\n" + "> > > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > ?\n" "> > > +Optional properties:\n" "> > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" "> > > +while probing. Should be a single cell.\n" "> > > +\n" - "> > > \302\240Example:\n" - "> > > \302\240\tinput-clk: input-clk {\n" - "> > > \302\240\t\tclock-frequency = <33333333>;\n" + "> > > ?Example:\n" + "> > > ?\tinput-clk: input-clk {\n" + "> > > ?\t\tclock-frequency = <33333333>;\n" "> > > @@ -25,4 +29,5 @@ Example:\n" - "> > > \302\240\t\treg = <0x80 0x10>, <0x100 0x10>;\n" - "> > > \302\240\t\t#clock-cells = <0>;\n" - "> > > \302\240\t\tclocks = <&input-clk>;\n" + "> > > ?\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> > > ?\t\t#clock-cells = <0>;\n" + "> > > ?\t\tclocks = <&input-clk>;\n" "> > > +\t\tclock-frequency = <100000000>;\n" - "> > > \302\240\t};\n" + "> > > ?\t};\n" "> > \n" "> > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt\n" "> > about how to assign initial clock rates, in general 'clock-frequency'\n" @@ -101,4 +93,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -0c1d2fd16334b509f53bc7c62d344e62314f85b66eafde6d603073d6fe20dcb3 +036c50438b1b65e5633633c534bcf06f0aa49a0c449c821ab317789d39f3ff43
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