diff for duplicates of <20171115032224.GG11163@dragon> diff --git a/a/1.txt b/N1/1.txt index 0509311..16b18bf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,10 +1,10 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: -> From: Younian Wang <wangyounian@hisilicon.com> +> From: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> > > Add pinctrl nodes for hi3798cv200-poplar board > -> Signed-off-by: Younian Wang <wangyounian@hisilicon.com> -> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> +> Signed-off-by: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> +> Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> > --- > .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 1 + > arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 71 +++ @@ -32,7 +32,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > #reset-cells = <2>; > }; > -> + pmx0: pinconf at 8a21000 { +> + pmx0: pinconf@8a21000 { > + compatible = "pinconf-single"; > + reg = <0x8a21000 0x180>; > + pinctrl-single,register-width = <32>; @@ -72,7 +72,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > + }; > + }; > + -> + pmx1: pinconf at 8000044 { +> + pmx1: pinconf@8000044 { > + compatible = "pinctrl-single"; > + reg = <0x8000044 4>; > + pinctrl-single,register-width = <32>; @@ -80,7 +80,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > + pinctrl-single,bit-per-mux; > + }; > + -> uart0: serial at 8b00000 { +> uart0: serial@8b00000 { > compatible = "arm,pl011", "arm,primecell"; > reg = <0x8b00000 0x1000>; > @@ -209,6 +257,7 @@ @@ -171,7 +171,7 @@ There is one cell number missing from the second phandle. It should be: Otherwise, we will see following error message in kernel boot log when this GPIO device gets enabled. - OF: /soc at f0000000/gpio at 8b29000: arguments longer than property + OF: /soc@f0000000/gpio@8b29000: arguments longer than property > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; @@ -879,4 +879,8 @@ Shawn > +}; > -- > 2.7.4 -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index ea9528c..6397285 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,27 @@ "ref\01508325728-55823-1-git-send-email-xuejiancheng@hisilicon.com\0" "ref\01508325728-55823-3-git-send-email-xuejiancheng@hisilicon.com\0" - "From\0shawn.guo@linaro.org (Shawn Guo)\0" - "Subject\0[PATCH 2/3] arm64: dts: hisilicon: add pinctrl nodes for hi3798cv200-poplar board\0" + "ref\01508325728-55823-3-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" + "From\0Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH 2/3] arm64: dts: hisilicon: add pinctrl nodes for hi3798cv200-poplar board\0" "Date\0Wed, 15 Nov 2017 11:22:27 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" + "Cc\0xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org" + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + project-aspen-dev-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + hermit.wangheming-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + " Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" "\00:1\0" "b\0" "On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote:\n" - "> From: Younian Wang <wangyounian@hisilicon.com>\n" + "> From: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" "> \n" "> Add pinctrl nodes for hi3798cv200-poplar board\n" "> \n" - "> Signed-off-by: Younian Wang <wangyounian@hisilicon.com>\n" - "> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>\n" + "> Signed-off-by: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" + "> Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" "> ---\n" "> .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 1 +\n" "> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 71 +++\n" @@ -40,7 +49,7 @@ "> \t\t\t#reset-cells = <2>;\n" "> \t\t};\n" "> \n" - "> +\t\tpmx0: pinconf at 8a21000 {\n" + "> +\t\tpmx0: pinconf@8a21000 {\n" "> +\t\t\tcompatible = \"pinconf-single\";\n" "> +\t\t\treg = <0x8a21000 0x180>;\n" "> +\t\t\tpinctrl-single,register-width = <32>;\n" @@ -80,7 +89,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tpmx1: pinconf at 8000044 {\n" + "> +\t\tpmx1: pinconf@8000044 {\n" "> +\t\t\tcompatible = \"pinctrl-single\";\n" "> +\t\t\treg = <0x8000044 4>;\n" "> +\t\t\tpinctrl-single,register-width = <32>;\n" @@ -88,7 +97,7 @@ "> +\t\t\tpinctrl-single,bit-per-mux;\n" "> +\t\t};\n" "> +\n" - "> \t\tuart0: serial at 8b00000 {\n" + "> \t\tuart0: serial@8b00000 {\n" "> \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> \t\t\treg = <0x8b00000 0x1000>;\n" "> @@ -209,6 +257,7 @@\n" @@ -179,7 +188,7 @@ "Otherwise, we will see following error message in kernel boot log when\n" "this GPIO device gets enabled.\n" "\n" - " OF: /soc at f0000000/gpio at 8b29000: arguments longer than property\n" + " OF: /soc@f0000000/gpio@8b29000: arguments longer than property\n" "\n" "> \t\t\tclocks = <&crg HISTB_APB_CLK>;\n" "> \t\t\tclock-names = \"apb_pclk\";\n" @@ -887,6 +896,10 @@ "> +};\n" "> -- \n" "> 2.7.4\n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -651b1a34d9a9f7efa3711b71c1e5bc14929da7945ec14a540512bfc83dd844f5 +4615572760c1ac2bb36a81f17ad136da41c8fc92db186a14c6facc65d8a0930c
diff --git a/a/1.txt b/N2/1.txt index 0509311..c5ae0f9 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -32,7 +32,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > #reset-cells = <2>; > }; > -> + pmx0: pinconf at 8a21000 { +> + pmx0: pinconf@8a21000 { > + compatible = "pinconf-single"; > + reg = <0x8a21000 0x180>; > + pinctrl-single,register-width = <32>; @@ -72,7 +72,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > + }; > + }; > + -> + pmx1: pinconf at 8000044 { +> + pmx1: pinconf@8000044 { > + compatible = "pinctrl-single"; > + reg = <0x8000044 4>; > + pinctrl-single,register-width = <32>; @@ -80,7 +80,7 @@ On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote: > + pinctrl-single,bit-per-mux; > + }; > + -> uart0: serial at 8b00000 { +> uart0: serial@8b00000 { > compatible = "arm,pl011", "arm,primecell"; > reg = <0x8b00000 0x1000>; > @@ -209,6 +257,7 @@ @@ -171,7 +171,7 @@ There is one cell number missing from the second phandle. It should be: Otherwise, we will see following error message in kernel boot log when this GPIO device gets enabled. - OF: /soc at f0000000/gpio at 8b29000: arguments longer than property + OF: /soc@f0000000/gpio@8b29000: arguments longer than property > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; diff --git a/a/content_digest b/N2/content_digest index ea9528c..94c95bd 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,17 @@ "ref\01508325728-55823-1-git-send-email-xuejiancheng@hisilicon.com\0" "ref\01508325728-55823-3-git-send-email-xuejiancheng@hisilicon.com\0" - "From\0shawn.guo@linaro.org (Shawn Guo)\0" - "Subject\0[PATCH 2/3] arm64: dts: hisilicon: add pinctrl nodes for hi3798cv200-poplar board\0" + "From\0Shawn Guo <shawn.guo@linaro.org>\0" + "Subject\0Re: [PATCH 2/3] arm64: dts: hisilicon: add pinctrl nodes for hi3798cv200-poplar board\0" "Date\0Wed, 15 Nov 2017 11:22:27 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jiancheng Xue <xuejiancheng@hisilicon.com>\0" + "Cc\0xuwei5@hisilicon.com" + robh+dt@kernel.org + linux-arm-kernel@lists.infradead.org + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + project-aspen-dev@linaro.org + hermit.wangheming@hisilicon.com + " Younian Wang <wangyounian@hisilicon.com>\0" "\00:1\0" "b\0" "On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote:\n" @@ -40,7 +48,7 @@ "> \t\t\t#reset-cells = <2>;\n" "> \t\t};\n" "> \n" - "> +\t\tpmx0: pinconf at 8a21000 {\n" + "> +\t\tpmx0: pinconf@8a21000 {\n" "> +\t\t\tcompatible = \"pinconf-single\";\n" "> +\t\t\treg = <0x8a21000 0x180>;\n" "> +\t\t\tpinctrl-single,register-width = <32>;\n" @@ -80,7 +88,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tpmx1: pinconf at 8000044 {\n" + "> +\t\tpmx1: pinconf@8000044 {\n" "> +\t\t\tcompatible = \"pinctrl-single\";\n" "> +\t\t\treg = <0x8000044 4>;\n" "> +\t\t\tpinctrl-single,register-width = <32>;\n" @@ -88,7 +96,7 @@ "> +\t\t\tpinctrl-single,bit-per-mux;\n" "> +\t\t};\n" "> +\n" - "> \t\tuart0: serial at 8b00000 {\n" + "> \t\tuart0: serial@8b00000 {\n" "> \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> \t\t\treg = <0x8b00000 0x1000>;\n" "> @@ -209,6 +257,7 @@\n" @@ -179,7 +187,7 @@ "Otherwise, we will see following error message in kernel boot log when\n" "this GPIO device gets enabled.\n" "\n" - " OF: /soc at f0000000/gpio at 8b29000: arguments longer than property\n" + " OF: /soc@f0000000/gpio@8b29000: arguments longer than property\n" "\n" "> \t\t\tclocks = <&crg HISTB_APB_CLK>;\n" "> \t\t\tclock-names = \"apb_pclk\";\n" @@ -889,4 +897,4 @@ "> 2.7.4\n" > -651b1a34d9a9f7efa3711b71c1e5bc14929da7945ec14a540512bfc83dd844f5 +17114acc03605f937b1e6ec5a3fa83d0ec0615043acce11eca874de65114c980
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