From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tvrtko Ursulin Subject: [RFC 2/2] drm/i915/pmu: Allow fine-grained PMU access control Date: Fri, 17 Nov 2017 13:57:23 +0000 Message-ID: <20171117135723.22235-2-tvrtko.ursulin@linux.intel.com> References: <20171117135723.22235-1-tvrtko.ursulin@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC88C6EA28 for ; Fri, 17 Nov 2017 13:57:34 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id r68so6663468wmr.1 for ; Fri, 17 Nov 2017 05:57:34 -0800 (PST) In-Reply-To: <20171117135723.22235-1-tvrtko.ursulin@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Intel-gfx@lists.freedesktop.org Cc: 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(majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934184AbdKQN5z (ORCPT ); Fri, 17 Nov 2017 08:57:55 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:35063 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934838AbdKQN5e (ORCPT ); Fri, 17 Nov 2017 08:57:34 -0500 X-Google-Smtp-Source: AGs4zMYORJv2rIB3NMKlvG0KiTc3YCFllN79sE1yT8+nilatxxizJHPkEiv3JCO6+JjKq3R4RQsJ1w== From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Tvrtko Ursulin , Dmitry Rogozhkin , Chris Wilson Subject: [RFC 2/2] drm/i915/pmu: Allow fine-grained PMU access control Date: Fri, 17 Nov 2017 13:57:23 +0000 Message-Id: <20171117135723.22235-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171117135723.22235-1-tvrtko.ursulin@linux.intel.com> References: <20171117135723.22235-1-tvrtko.ursulin@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tvrtko Ursulin We implement the new pmu->is_privileged callback and add our own sysctl as /proc/sys/dev/i915/pmu_stream_paranoid (defaulting to true), which enables system administrators to override the global /proc/sys/kernel/perf_event_paranoid setting for i915 PMU only. Signed-off-by: Tvrtko Ursulin Cc: Dmitry Rogozhkin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_pmu.c | 55 +++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_pmu.h | 4 +++ 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index baa663641bb7..a8eca7303b7e 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -43,6 +43,11 @@ static cpumask_t i915_pmu_cpumask = CPU_MASK_NONE; +/* for sysctl proc_dointvec_minmax of dev.i915.pmu_stream_paranoid */ +static int zero; +static int one = 1; +static u32 i915_pmu_stream_paranoid = true; + static u8 engine_config_sample(u64 config) { return config & I915_PMU_SAMPLE_MASK; @@ -647,6 +652,11 @@ static int i915_pmu_event_event_idx(struct perf_event *event) return 0; } +static bool i915_pmu_is_privileged(struct perf_event *event) +{ + return i915_pmu_stream_paranoid; +} + static ssize_t i915_pmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -834,11 +844,44 @@ static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915) #endif } +static struct ctl_table pmu_table[] = { + { + .procname = "pmu_stream_paranoid", + .data = &i915_pmu_stream_paranoid, + .maxlen = sizeof(i915_pmu_stream_paranoid), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, + }, + {} +}; + +static struct ctl_table i915_root[] = { + { + .procname = "i915", + .maxlen = 0, + .mode = 0555, + .child = pmu_table, + }, + {} +}; + +static struct ctl_table dev_root[] = { + { + .procname = "dev", + .maxlen = 0, + .mode = 0555, + .child = i915_root, + }, + {} +}; + void i915_pmu_register(struct drm_i915_private *i915) { struct intel_engine_cs *engine; enum intel_engine_id id; - int ret; + int ret = -EINVAL; if (INTEL_GEN(i915) <= 2) { DRM_INFO("PMU not supported for this GPU."); @@ -854,6 +897,7 @@ void i915_pmu_register(struct drm_i915_private *i915) i915->pmu.base.stop = i915_pmu_event_stop; i915->pmu.base.read = i915_pmu_event_read; i915->pmu.base.event_idx = i915_pmu_event_event_idx; + i915->pmu.base.is_privileged = i915_pmu_is_privileged; spin_lock_init(&i915->pmu.lock); hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); @@ -863,9 +907,12 @@ void i915_pmu_register(struct drm_i915_private *i915) INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats, __disable_busy_stats); + if (!(i915->pmu.sysctl_header = register_sysctl_table(dev_root))) + goto err; + ret = perf_pmu_register(&i915->pmu.base, "i915", -1); if (ret) - goto err; + goto err_pmu; ret = i915_pmu_register_cpuhp_state(i915); if (ret) @@ -875,6 +922,8 @@ void i915_pmu_register(struct drm_i915_private *i915) err_unreg: perf_pmu_unregister(&i915->pmu.base); +err_pmu: + unregister_sysctl_table(i915->pmu.sysctl_header); err: i915->pmu.base.event_init = NULL; DRM_NOTE("Failed to register PMU! (err=%d)\n", ret); @@ -899,6 +948,8 @@ void i915_pmu_unregister(struct drm_i915_private *i915) i915_pmu_unregister_cpuhp_state(i915); + unregister_sysctl_table(i915->pmu.sysctl_header); + perf_pmu_unregister(&i915->pmu.base); i915->pmu.base.event_init = NULL; } diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index e209783a4c5f..30e2192b4218 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -61,6 +61,10 @@ struct i915_pmu { * @timer: Timer for internal i915 PMU sampling. */ struct hrtimer timer; + /** + * @sysctl_header: Sysctl table header. + */ + struct ctl_table_header *sysctl_header; /** * @enable: Bitmask of all currently enabled events. * -- 2.14.1