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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>,
	bhelgaas@google.com, linux-pci@vger.kernel.org,
	adouglas@cadence.com, stelford@cadence.com, dgary@cadence.com,
	kgopi@cadence.com, eandrews@cadence.com,
	thomas.petazzoni@free-electrons.com, sureshp@cadence.com,
	nsekhar@ti.com, linux-kernel@vger.kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 0/5] PCI: Add support to the Cadence PCIe controller
Date: Thu, 30 Nov 2017 18:18:19 +0000	[thread overview]
Message-ID: <20171130181819.GD12096@red-moon> (raw)
In-Reply-To: <8c6c50fc-47a9-7b93-d826-1dba9c4d09c2@ti.com>

On Thu, Nov 30, 2017 at 12:43:20PM +0530, Kishon Vijay Abraham I wrote:

[...]

> >> For linux-next, I applied this series on top of Kishon's patch
> >> ("PCI: endpoint: Use EPC's device in dma_alloc_coherent/dma_free_coherent")
> >> otherwise dma_alloc_coherent() fails when called by pci_epf_alloc_space().
> >>
> >> Also, I patched drivers/Makefile rather than drivers/pci/Makefile to make
> >> the drivers/pci/cadence/pcie-cadence-ep.o linked after
> 
> The reason to patch drivers/Makefile should be because pcie-cadence-ep has to
> be compiled even when CONFIG_PCI is not enabled. CONFIG_PCI enables host
> specific features and ENDPOINT shouldn't depend on CONFIG_PCI.
> >> drivers/pci/endpoint/*.o objects, otherwise the built-in pci-cadence-ep
> >> driver would be probed before the PCI endpoint framework would have been
> >> initialized, which results in a kernel crash.
> > 
> > Nice :( - isn't there a way to improve this (ie probe deferral or
> > registering the EPF bus earlier) ?
> > 
> >> I guess this is the reason why the "pci/dwc" line was also put in
> >> drivers/Makefile, right after the "pci/endpoint" line.
> > 
> > Or probably the other way around - see commit 5e8cb4033807
> > 
> > @Kishon, thoughts ?
> 
> Lorenzo, ordering Makefile is one way to initialize EP core before

Makefile ordering is fragile, I do not like relying on it.

> other drivers. the other way is to have PCI EP core have a different
> initcall level..  subsys_initcall??

Yes, registering the bus at eg postcore_initcall() as PCI does should do
(if that's the problem this is solving) but still, the code must not
crash if the ordering is not correct, we have to fix this regardless.

I would appreciate if Cyrille can debug the cause of the kernel crash
so that we can fix it in the longer term.

Thanks,
Lorenzo

  reply	other threads:[~2017-11-30 18:18 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-23 15:01 [PATCH 0/5] PCI: Add support to the Cadence PCIe controller Cyrille Pitchen
2017-11-23 15:01 ` [PATCH 1/5] PCI: Add vendor ID for Cadence Cyrille Pitchen
2017-11-23 15:01   ` Cyrille Pitchen
2017-12-06 21:27   ` Bjorn Helgaas
2017-12-06 21:27     ` Bjorn Helgaas
2017-11-23 15:01 ` [PATCH 2/5] dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller Cyrille Pitchen
2017-11-26 19:32   ` Rob Herring
2017-11-26 19:32     ` Rob Herring
2017-11-23 15:01 ` [PATCH 3/5] PCI: cadence: Add host driver for Cadence PCIe controller Cyrille Pitchen
2017-11-23 15:01   ` Cyrille Pitchen
2017-11-28 20:41   ` Bjorn Helgaas
2017-11-28 20:46     ` Bjorn Helgaas
2017-11-29  8:19     ` Thomas Petazzoni
2017-11-29  8:19       ` Thomas Petazzoni
2017-11-29 15:55       ` Bjorn Helgaas
2017-11-29 14:14     ` Lorenzo Pieralisi
2017-12-01 10:37     ` Cyrille Pitchen
2017-12-01 10:37       ` Cyrille Pitchen
2017-12-01 16:20       ` Lorenzo Pieralisi
2017-12-01 16:20         ` Lorenzo Pieralisi
2017-11-29 17:34   ` Lorenzo Pieralisi
2017-11-29 17:34     ` Lorenzo Pieralisi
2017-12-03 20:44     ` Cyrille Pitchen
2017-12-04 18:20       ` Lorenzo Pieralisi
2017-12-04 18:49         ` Ard Biesheuvel
2017-12-06 11:32           ` Lorenzo Pieralisi
2017-12-06 11:32             ` Lorenzo Pieralisi
2017-12-13 16:42             ` Cyrille Pitchen
2017-11-29 18:25   ` Lorenzo Pieralisi
2017-11-30 10:06     ` Lorenzo Pieralisi
2017-11-23 15:01 ` [PATCH 4/5] dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller Cyrille Pitchen
2017-11-26 19:33   ` Rob Herring
2017-11-23 15:01 ` [PATCH 5/5] PCI: cadence: add EndPoint Controller driver for Cadence PCIe controller Cyrille Pitchen
2017-12-01 12:20   ` Lorenzo Pieralisi
2017-12-04 14:56     ` Cyrille Pitchen
2017-12-05  9:19     ` Kishon Vijay Abraham I
2017-12-05  9:19       ` Kishon Vijay Abraham I
2017-12-07 10:05       ` Philippe Ombredanne
2017-12-13 16:03         ` Cyrille Pitchen
2017-12-13 16:03           ` Cyrille Pitchen
2017-12-13 16:50       ` Cyrille Pitchen
2017-12-13 16:50         ` Cyrille Pitchen
2017-12-14 17:03         ` Cyrille Pitchen
2017-12-15  5:49           ` Kishon Vijay Abraham I
2017-12-15  5:49             ` Kishon Vijay Abraham I
2017-12-15 11:49             ` Cyrille Pitchen
2017-12-15 11:49               ` Cyrille Pitchen
2017-11-28 15:50 ` [PATCH 0/5] PCI: Add support to the " Lorenzo Pieralisi
2017-11-30  7:13   ` Kishon Vijay Abraham I
2017-11-30  7:13     ` Kishon Vijay Abraham I
2017-11-30 18:18     ` Lorenzo Pieralisi [this message]
2017-11-30 18:45       ` Cyrille Pitchen
2017-11-30 20:05         ` Cyrille Pitchen
2017-11-30 20:05           ` Cyrille Pitchen
2017-11-30 23:05           ` Bjorn Helgaas

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