From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 6/8] drm/i915: Add function to output Aksv over GMBUS Date: Fri, 1 Dec 2017 22:03:38 +0200 Message-ID: <20171201200338.GN10981@intel.com> References: <20171201172032.47357-1-seanpaul@chromium.org> <20171201172032.47357-7-seanpaul@chromium.org> <20171201190614.GM10981@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul Cc: David Airlie , Intel Graphics Development , Joonas Lahtinen , Linux Kernel Mailing List , dri-devel , Rodrigo Vivi , Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gRnJpLCBEZWMgMDEsIDIwMTcgYXQgMDI6MTc6MTlQTSAtMDUwMCwgU2VhbiBQYXVsIHdyb3Rl Ogo+IE9uIEZyaSwgRGVjIDEsIDIwMTcgYXQgMjowNiBQTSwgVmlsbGUgU3lyasOkbMOkCj4gPHZp bGxlLnN5cmphbGFAbGludXguaW50ZWwuY29tPiB3cm90ZToKPiA+IE9uIEZyaSwgRGVjIDAxLCAy MDE3IGF0IDEyOjIwOjI4UE0gLTA1MDAsIFNlYW4gUGF1bCB3cm90ZToKPiA+PiBPbmNlIHRoZSBB a3N2IGlzIGF2YWlsYWJsZSBpbiB0aGUgUENILCB3ZSBuZWVkIHRvIGdldCBpdCBvbiB0aGUgd2ly ZSB0bwo+ID4+IHRoZSByZWNlaXZlciB2aWEgRERDLiBUaGUgaGFyZHdhcmUgZG9lc24ndCBhbGxv dyB1cyB0byByZWFkIHRoZSB2YWx1ZQo+ID4+IGRpcmVjdGx5LCBzbyB3ZSBuZWVkIHRvIHRlbGwg R01CVVMgdG8gc291cmNlIHRoZSBBa3N2IGludGVybmFsbHkgYW5kCj4gPj4gc2VuZCBpdCB0byB0 aGUgcmlnaHQgb2Zmc2V0IG9uIHRoZSByZWNlaXZlci4KPiA+Pgo+ID4+IFRoZSB3YXkgd2UgZG8g dGhpcyBpcyB0byBpbml0aWF0ZSBhbiBpbmRleGVkIHdyaXRlIHdoZXJlIHRoZSBpbmRleCBpcwo+ ID4+IHRoZSBBa3N2IHJlZ2lzdGVyIG9mZnNldC4gV2Ugd3JpdGUgZHVtbXkgdmFsdWVzIHRvIEdN QlVTMyBhcyBpZiB3ZSB3ZXJlCj4gPj4gc2VuZGluZyB0aGUga2V5LCBhbmQgdGhlIGhhcmR3YXJl IHNsaXBzIGluIHRoZSAicmVhbCIgdmFsdWVzIHdoZW4gaXQKPiA+PiBnb2VzIG91dC4KPiA+Pgo+ ID4+IENoYW5nZXMgaW4gdjI6Cj4gPj4gLSBOb25lCj4gPj4KPiA+PiBTaWduZWQtb2ZmLWJ5OiBT ZWFuIFBhdWwgPHNlYW5wYXVsQGNocm9taXVtLm9yZz4KPiA+PiAtLS0KPiA+PiAgZHJpdmVycy9n cHUvZHJtL2k5MTUvaTkxNV9kcnYuaCAgfCAgMSArCj4gPj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1 L2k5MTVfcmVnLmggIHwgIDEgKwo+ID4+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9pMmMu YyB8IDU0ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKystLS0tLS0KPiA+PiAgMyBm aWxlcyBjaGFuZ2VkLCA0OCBpbnNlcnRpb25zKCspLCA4IGRlbGV0aW9ucygtKQo+ID4+Cj4gPj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmggYi9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pOTE1X2Rydi5oCj4gPj4gaW5kZXggMzZiYjQ5Mjc0ODRhLi4xMGY3NDBjOWU1 NzEgMTAwNjQ0Cj4gPj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaAo+ID4+ ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmgKPiA+PiBAQCAtNDA0Myw2ICs0 MDQzLDcgQEAgZXh0ZXJuIGludCBpbnRlbF9zZXR1cF9nbWJ1cyhzdHJ1Y3QgZHJtX2k5MTVfcHJp dmF0ZSAqZGV2X3ByaXYpOwo+ID4+ICBleHRlcm4gdm9pZCBpbnRlbF90ZWFyZG93bl9nbWJ1cyhz dHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYpOwo+ID4+ICBleHRlcm4gYm9vbCBpbnRl bF9nbWJ1c19pc192YWxpZF9waW4oc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgdW5zaWduZWQgaW50IHBpbik7 Cj4gPj4gK2V4dGVybiBpbnQgaW50ZWxfZ21idXNfb3V0cHV0X2Frc3Yoc3RydWN0IGkyY19hZGFw dGVyICphZGFwdGVyKTsKPiA+Pgo+ID4+ICBleHRlcm4gc3RydWN0IGkyY19hZGFwdGVyICoKPiA+ PiAgaW50ZWxfZ21idXNfZ2V0X2FkYXB0ZXIoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9w cml2LCB1bnNpZ25lZCBpbnQgcGluKTsKPiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L2k5MTUvaTkxNV9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiA+PiBp bmRleCA2ZGNhMzA1Y2NiZjcuLjhiNzFhMjA4ODJjYSAxMDA2NDQKPiA+PiAtLS0gYS9kcml2ZXJz L2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gPj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aTkxNV9yZWcuaAo+ID4+IEBAIC0zMDQwLDYgKzMwNDAsNyBAQCBlbnVtIGk5MTVfcG93ZXJfd2Vs bF9pZCB7Cj4gPj4gICMgZGVmaW5lIEdQSU9fREFUQV9QVUxMVVBfRElTQUJMRSAgICAoMSA8PCAx MykKPiA+Pgo+ID4+ICAjZGVmaW5lIEdNQlVTMCAgICAgICAgICAgICAgICAgICAgICAgX01NSU8o ZGV2X3ByaXYtPmdwaW9fbW1pb19iYXNlICsgMHg1MTAwKSAvKiBjbG9jay9wb3J0IHNlbGVjdCAq Lwo+ID4+ICsjZGVmaW5lICAgR01CVVNfQUtTVl9TRUxFQ1QgICgxPDwxMSkKPiA+PiAgI2RlZmlu ZSAgIEdNQlVTX1JBVEVfMTAwS0haICAoMDw8OCkKPiA+PiAgI2RlZmluZSAgIEdNQlVTX1JBVEVf NTBLSFogICAoMTw8OCkKPiA+PiAgI2RlZmluZSAgIEdNQlVTX1JBVEVfNDAwS0haICAoMjw8OCkg LyogcmVzZXJ2ZWQgb24gUGluZXZpZXcgKi8KPiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUv ZHJtL2k5MTUvaW50ZWxfaTJjLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9pMmMuYwo+ ID4+IGluZGV4IGViNTgyNzExMGQ4Zi4uYzAxMTU2YmYwZjI3IDEwMDY0NAo+ID4+IC0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2kyYy5jCj4gPj4gKysrIGIvZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfaTJjLmMKPiA+PiBAQCAtMzAsNiArMzAsNyBAQAo+ID4+ICAjaW5jbHVkZSA8 bGludXgvaTJjLWFsZ28tYml0Lmg+Cj4gPj4gICNpbmNsdWRlIDxsaW51eC9leHBvcnQuaD4KPiA+ PiAgI2luY2x1ZGUgPGRybS9kcm1QLmg+Cj4gPj4gKyNpbmNsdWRlIDxkcm0vZHJtX2hkY3AuaD4K PiA+PiAgI2luY2x1ZGUgImludGVsX2Rydi5oIgo+ID4+ICAjaW5jbHVkZSA8ZHJtL2k5MTVfZHJt Lmg+Cj4gPj4gICNpbmNsdWRlICJpOTE1X2Rydi5oIgo+ID4+IEBAIC0zNzMsNyArMzc0LDggQEAg Z21idXNfeGZlcl9yZWFkKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwgc3RydWN0 IGkyY19tc2cgKm1zZywKPiA+Pgo+ID4+ICBzdGF0aWMgaW50Cj4gPj4gIGdtYnVzX3hmZXJfd3Jp dGVfY2h1bmsoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ID4+IC0gICAgICAg ICAgICAgICAgICAgIHVuc2lnbmVkIHNob3J0IGFkZHIsIHU4ICpidWYsIHVuc2lnbmVkIGludCBs ZW4pCj4gPj4gKyAgICAgICAgICAgICAgICAgICAgdW5zaWduZWQgc2hvcnQgYWRkciwgdTggKmJ1 ZiwgdW5zaWduZWQgaW50IGxlbiwKPiA+PiArICAgICAgICAgICAgICAgICAgICB1MzIgZ21idXMx X2luZGV4KQo+ID4+ICB7Cj4gPj4gICAgICAgdW5zaWduZWQgaW50IGNodW5rX3NpemUgPSBsZW47 Cj4gPj4gICAgICAgdTMyIHZhbCwgbG9vcDsKPiA+PiBAQCAtMzg2LDcgKzM4OCw3IEBAIGdtYnVz X3hmZXJfd3JpdGVfY2h1bmsoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ID4+ Cj4gPj4gICAgICAgSTkxNV9XUklURV9GVyhHTUJVUzMsIHZhbCk7Cj4gPj4gICAgICAgSTkxNV9X UklURV9GVyhHTUJVUzEsCj4gPj4gLSAgICAgICAgICAgICAgICAgICBHTUJVU19DWUNMRV9XQUlU IHwKPiA+PiArICAgICAgICAgICAgICAgICAgIGdtYnVzMV9pbmRleCB8IEdNQlVTX0NZQ0xFX1dB SVQgfAo+ID4+ICAgICAgICAgICAgICAgICAgICAgKGNodW5rX3NpemUgPDwgR01CVVNfQllURV9D T1VOVF9TSElGVCkgfAo+ID4+ICAgICAgICAgICAgICAgICAgICAgKGFkZHIgPDwgR01CVVNfU0xB VkVfQUREUl9TSElGVCkgfAo+ID4+ICAgICAgICAgICAgICAgICAgICAgR01CVVNfU0xBVkVfV1JJ VEUgfCBHTUJVU19TV19SRFkpOwo+ID4+IEBAIC00MDksNyArNDExLDggQEAgZ21idXNfeGZlcl93 cml0ZV9jaHVuayhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCj4gPj4gIH0KPiA+ Pgo+ID4+ICBzdGF0aWMgaW50Cj4gPj4gLWdtYnVzX3hmZXJfd3JpdGUoc3RydWN0IGRybV9pOTE1 X3ByaXZhdGUgKmRldl9wcml2LCBzdHJ1Y3QgaTJjX21zZyAqbXNnKQo+ID4+ICtnbWJ1c194ZmVy X3dyaXRlKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwgc3RydWN0IGkyY19tc2cg Km1zZywKPiA+PiArICAgICAgICAgICAgICB1MzIgZ21idXMxX2luZGV4KQo+ID4+ICB7Cj4gPj4g ICAgICAgdTggKmJ1ZiA9IG1zZy0+YnVmOwo+ID4+ICAgICAgIHVuc2lnbmVkIGludCB0eF9zaXpl ID0gbXNnLT5sZW47Cj4gPj4gQEAgLTQxOSw3ICs0MjIsOCBAQCBnbWJ1c194ZmVyX3dyaXRlKHN0 cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwgc3RydWN0IGkyY19tc2cgKm1zZykKPiA+ PiAgICAgICBkbyB7Cj4gPj4gICAgICAgICAgICAgICBsZW4gPSBtaW4odHhfc2l6ZSwgR01CVVNf QllURV9DT1VOVF9NQVgpOwo+ID4+Cj4gPj4gLSAgICAgICAgICAgICByZXQgPSBnbWJ1c194ZmVy X3dyaXRlX2NodW5rKGRldl9wcml2LCBtc2ctPmFkZHIsIGJ1ZiwgbGVuKTsKPiA+PiArICAgICAg ICAgICAgIHJldCA9IGdtYnVzX3hmZXJfd3JpdGVfY2h1bmsoZGV2X3ByaXYsIG1zZy0+YWRkciwg YnVmLCBsZW4sCj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IGdtYnVzMV9pbmRleCk7Cj4gPj4gICAgICAgICAgICAgICBpZiAocmV0KQo+ID4+ICAgICAgICAg ICAgICAgICAgICAgICByZXR1cm4gcmV0Owo+ID4+Cj4gPj4gQEAgLTQ3MCw3ICs0NzQsOCBAQCBn bWJ1c194ZmVyX2luZGV4X3JlYWQoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LCBz dHJ1Y3QgaTJjX21zZyAqbXNncykKPiA+PiAgfQo+ID4+Cj4gPj4gIHN0YXRpYyBpbnQKPiA+PiAt ZG9fZ21idXNfeGZlcihzdHJ1Y3QgaTJjX2FkYXB0ZXIgKmFkYXB0ZXIsIHN0cnVjdCBpMmNfbXNn ICptc2dzLCBpbnQgbnVtKQo+ID4+ICtkb19nbWJ1c194ZmVyKHN0cnVjdCBpMmNfYWRhcHRlciAq YWRhcHRlciwgc3RydWN0IGkyY19tc2cgKm1zZ3MsIGludCBudW0sCj4gPj4gKyAgICAgICAgICAg dTMyIGdtYnVzMF9zb3VyY2UsIHUzMiBnbWJ1czFfaW5kZXgpCj4gPj4gIHsKPiA+PiAgICAgICBz dHJ1Y3QgaW50ZWxfZ21idXMgKmJ1cyA9IGNvbnRhaW5lcl9vZihhZGFwdGVyLAo+ID4+ICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHN0cnVjdCBpbnRlbF9nbWJ1 cywKPiA+PiBAQCAtNDgwLDcgKzQ4NSw3IEBAIGRvX2dtYnVzX3hmZXIoc3RydWN0IGkyY19hZGFw dGVyICphZGFwdGVyLCBzdHJ1Y3QgaTJjX21zZyAqbXNncywgaW50IG51bSkKPiA+PiAgICAgICBp bnQgcmV0ID0gMDsKPiA+Pgo+ID4+ICByZXRyeToKPiA+PiAtICAgICBJOTE1X1dSSVRFX0ZXKEdN QlVTMCwgYnVzLT5yZWcwKTsKPiA+PiArICAgICBJOTE1X1dSSVRFX0ZXKEdNQlVTMCwgZ21idXMw X3NvdXJjZSB8IGJ1cy0+cmVnMCk7Cj4gPj4KPiA+PiAgICAgICBmb3IgKDsgaSA8IG51bTsgaSAr PSBpbmMpIHsKPiA+PiAgICAgICAgICAgICAgIGluYyA9IDE7Cj4gPj4gQEAgLTQ5MCw3ICs0OTUs OCBAQCBkb19nbWJ1c194ZmVyKHN0cnVjdCBpMmNfYWRhcHRlciAqYWRhcHRlciwgc3RydWN0IGky Y19tc2cgKm1zZ3MsIGludCBudW0pCj4gPj4gICAgICAgICAgICAgICB9IGVsc2UgaWYgKG1zZ3Nb aV0uZmxhZ3MgJiBJMkNfTV9SRCkgewo+ID4+ICAgICAgICAgICAgICAgICAgICAgICByZXQgPSBn bWJ1c194ZmVyX3JlYWQoZGV2X3ByaXYsICZtc2dzW2ldLCAwKTsKPiA+PiAgICAgICAgICAgICAg IH0gZWxzZSB7Cj4gPj4gLSAgICAgICAgICAgICAgICAgICAgIHJldCA9IGdtYnVzX3hmZXJfd3Jp dGUoZGV2X3ByaXYsICZtc2dzW2ldKTsKPiA+PiArICAgICAgICAgICAgICAgICAgICAgcmV0ID0g Z21idXNfeGZlcl93cml0ZShkZXZfcHJpdiwgJm1zZ3NbaV0sCj4gPj4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZ21idXMxX2luZGV4KTsKPiA+PiAgICAgICAg ICAgICAgIH0KPiA+Pgo+ID4+ICAgICAgICAgICAgICAgaWYgKCFyZXQpCj4gPj4gQEAgLTU5OCw3 ICs2MDQsNyBAQCBnbWJ1c194ZmVyKHN0cnVjdCBpMmNfYWRhcHRlciAqYWRhcHRlciwgc3RydWN0 IGkyY19tc2cgKm1zZ3MsIGludCBudW0pCj4gPj4gICAgICAgICAgICAgICBpZiAocmV0IDwgMCkK PiA+PiAgICAgICAgICAgICAgICAgICAgICAgYnVzLT5mb3JjZV9iaXQgJj0gfkdNQlVTX0ZPUkNF X0JJVF9SRVRSWTsKPiA+PiAgICAgICB9IGVsc2Ugewo+ID4+IC0gICAgICAgICAgICAgcmV0ID0g ZG9fZ21idXNfeGZlcihhZGFwdGVyLCBtc2dzLCBudW0pOwo+ID4+ICsgICAgICAgICAgICAgcmV0 ID0gZG9fZ21idXNfeGZlcihhZGFwdGVyLCBtc2dzLCBudW0sIDAsIDApOwo+ID4+ICAgICAgICAg ICAgICAgaWYgKHJldCA9PSAtRUFHQUlOKQo+ID4+ICAgICAgICAgICAgICAgICAgICAgICBidXMt PmZvcmNlX2JpdCB8PSBHTUJVU19GT1JDRV9CSVRfUkVUUlk7Cj4gPj4gICAgICAgfQo+ID4+IEBA IC02MDgsNiArNjE0LDM4IEBAIGdtYnVzX3hmZXIoc3RydWN0IGkyY19hZGFwdGVyICphZGFwdGVy LCBzdHJ1Y3QgaTJjX21zZyAqbXNncywgaW50IG51bSkKPiA+PiAgICAgICByZXR1cm4gcmV0Owo+ ID4+ICB9Cj4gPj4KPiA+PiAraW50IGludGVsX2dtYnVzX291dHB1dF9ha3N2KHN0cnVjdCBpMmNf YWRhcHRlciAqYWRhcHRlcikKPiA+PiArewo+ID4+ICsgICAgIHN0cnVjdCBpbnRlbF9nbWJ1cyAq YnVzID0gY29udGFpbmVyX29mKGFkYXB0ZXIsIHN0cnVjdCBpbnRlbF9nbWJ1cywKPiA+PiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBhZGFwdGVyKTsKPiA+PiAr ICAgICBzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYgPSBidXMtPmRldl9wcml2Owo+ ID4+ICsgICAgIGludCByZXQ7Cj4gPj4gKyAgICAgdTggYnVmW0RSTV9IRENQX0tTVl9MRU5dID0g eyAwIH07Cj4gPj4gKyAgICAgc3RydWN0IGkyY19tc2cgbXNnID0gewo+ID4+ICsgICAgICAgICAg ICAgLmFkZHIgPSBEUk1fSERDUF9ERENfQUREUiwKPiA+PiArICAgICAgICAgICAgIC5mbGFncyA9 IDAsCj4gPj4gKyAgICAgICAgICAgICAubGVuID0gc2l6ZW9mKGJ1ZiksCj4gPj4gKyAgICAgICAg ICAgICAuYnVmID0gYnVmLAo+ID4+ICsgICAgIH07Cj4gPj4gKwo+ID4+ICsgICAgIGludGVsX2Rp c3BsYXlfcG93ZXJfZ2V0KGRldl9wcml2LCBQT1dFUl9ET01BSU5fR01CVVMpOwo+ID4+ICsgICAg IG11dGV4X2xvY2soJmRldl9wcml2LT5nbWJ1c19tdXRleCk7Cj4gPj4gKwo+ID4+ICsgICAgIC8q Cj4gPj4gKyAgICAgICogSW4gb3JkZXIgdG8gb3V0cHV0IEFrc3YgdG8gdGhlIHJlY2VpdmVyLCB1 c2UgYW4gaW5kZXhlZCB3cml0ZSB0bwo+ID4+ICsgICAgICAqIHBhc3MgdGhlIGkyYyBjb21tYW5k LCBhbmQgdGVsbCBHTUJVUyB0byB1c2UgdGhlIEhXLXByb3ZpZGVkIHZhbHVlCj4gPj4gKyAgICAg ICogaW5zdGVhZCBvZiBzb3VyY2luZyBHTUJVUzMgZm9yIHRoZSBkYXRhLgo+ID4+ICsgICAgICAq Lwo+ID4+ICsgICAgIHJldCA9IGRvX2dtYnVzX3hmZXIoYWRhcHRlciwgJm1zZywgMSwgR01CVVNf QUtTVl9TRUxFQ1QsCj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICBHTUJVU19DWUNMRV9J TkRFWCB8Cj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAoRFJNX0hEQ1BfRERDX0FLU1Yg PDwgR01CVVNfU0xBVkVfSU5ERVhfU0hJRlQpKTsKPiA+Cj4gPiBJdCBtaWdodCBiZSBuaWNlciB0 byBqdXN0IHVzZSB0d28gbXNncyBoZXJlIGFuZCBtb2RpZnkKPiA+IGdtYnVzX3hmZXJfaW5kZXhf cmVhZCgpIHRvIHN1cHBvcnQgaW5kZXhlZCB3cml0ZXMgYXMgd2VsbC4KPiAKPiBJIHRoaW5rIHR3 byBtc2dzIGltcGxpZXMgYSBTVE9QIGJpdCBpbiBiZXR3ZWVuLiBBdCBsZWFzdCwgdGhhdCdzIGhv dyBJCj4gaW50ZXJwcmV0ICJub3JtYWwiIHdyaXRlcy4KClRoZXJlIGlzIG5ldmVyIGEgc3RlcCBi ZXR3ZWVuIHR3byBtc2dzIEFJVUksIHVubGVzcyB5b3Ugc3BlY2lmeQpJMkNfTV9TVE9QLiBUaGVy ZSBtaWdodCBiZSBhIHJlcGVhdGVkIHN0YXJ0LiBJZiB3ZSB3YW50IHRvIGJlIHBlZGFudGljCmFi b3V0IHRoZSByZXBlYXRlZCBzdGFydCB3ZSBjb3VsZCB1c2UgdGhlIEkyQ19NX05PU1RBUlQgZmxh Zy4gQWx0aG91Z2gKSSBkb24ndCB0aGluayB0aGlzIHN0dWZmIGlzIHJlYWxseSBkb2N1bWVudGVk IGFueXdoZXJlIHNvIEknbSBub3Qgc3VyZQppZiBJMkNfTV9OT1NUQVJUIGlzIHJlYWxseSBzdXBw b3NlZCB0byBhcHBseSB0byB0d28gbWVzc2FnZXMgd2l0aCB0aGUKc2FtZSBzbGF2ZSBhZGRyZXNz IGFuZCBzYW1lIGRpcmVjdGlvbiwgb3IgaWYgaXQncyBqdXN0IG1lYW50IHRvCnN1cHByZXNzIHRo ZSByZXBlYXRlZCBzdGFydCB3aGVuIGNoYW5naW5nIHRoZSBkaXJlY3Rpb24gb2YgdGhlIGJ1cwoo d2hpY2ggZ21idXMgY2FuJ3QgZG8sIGFuZCB3ZSBhY3R1YWxseSBmYWlsIHRvIGNoZWNrIGZvciB0 aGF0KS4KCkkgc3VwcG9zZSBpMmMtYWxnby1iaXQgaXMgdGhlIGRlZmFjdG8gc3RhbmRhcmQgaGVy ZS4gQW5kIHRoYXQgb25lCnNlZW1zIHRvIGRvIHRoZSByZXBlYXRlZCBzdGFydCB3aGVuZXZlciBJ MkNfTV9OT1NUQVJUIGlzIG5vdCBzcGVjaWZpZWQuCldvdWxkIGJlIGFjdHVhbGx5IG5pY2UgdG8g a25vdyB3aGF0IGdtYnVzIGRvZXMgd2hlbiB5b3UganVzdCBkbyB0d28KYmFjayB0byBiYWNrIG5v bi1pbmRleGVkIHdyaXRlcyB0byB0aGUgc2FtZSBzbGF2ZSBhZGRyZXNzLiBJZiBpdApkb2Vzbid0 IGRvIGEgcmVwZWF0ZWQgc3RhcnQgaW4gYmV0d2VlbiwgdGhlbiBJIGd1ZXNzIHdlJ3JlIGFsc28K dmlvbGF0aW5nIEkyQ19NX05PU1RBUlQgY3VycmVudGx5LgoKPiAKPiA+IFdvdWxkIGF2b2lkIGhh dmluZyB0byBwYXNzIGluIHRoZSBHTUJVUzEgdmFsdWUgYWxsIHRoZSB3YXkuCj4gCj4gV2UgY291 bGQgaW5mZXIgYW4gaW5kZXhlZCB3cml0ZSBpZiBudW1fbXNncyA9PSAxICYmIGZsYWdzID09IDAg JiYgbGVuCj4gPiAxLiBIb3dldmVyIHRoYXQgd291bGQgcmVxdWlyZSB1cyB0byBhc3N1bWUgdGhh dCBhbGwgc2luZ2xlIG1zZwo+IHdyaXRlcyBoYXZlIGEgY29tbWFuZCBieXRlIGF0IHRoZSBiZWdp bm5pbmcgb2YgdGhlIHRyYW5zYWN0aW9uLCB3aGljaAo+IG1pZ2h0IG5vdCBiZSB0cnVlIGZvciBh bGwgaTJjIHNsYXZlcy4KPiAKPiBTZWFuCj4gCj4gCj4gPgo+ID4gTm90IHN1cmUgd2hhdCB0byBk byB3aXRoIEdNQlVTX0FLU1ZfU0VMRUNULiBJIGd1ZXNzIGVpdGhlciBwYXNzCj4gPiBpdCBpbiBl eHBsaWNpdGx5IGxpa2UgeW91J3JlIGRvaW5nIGhlcmUsIG9yIG1heWJlIGFkZCBhIHNtYWxsCj4g PiBoZWxwZXIgYWxhIGdtYnVzX2lzX2luZGV4X3JlYWQoKSBzbyB0aGF0IGRvX2dtYnVzX3hmZXIo KSBjb3VsZAo+ID4gc25pZmYgb3V0IHdoaWNoIHNvdXJjZSB3ZSBzaG91bGQgdXNlIGJhc2VkIG9u IHRoZSBwYXNzZWQgaW4gbXNncz8KPiA+Cj4gPj4gKwo+ID4+ICsgICAgIG11dGV4X3VubG9jaygm ZGV2X3ByaXYtPmdtYnVzX211dGV4KTsKPiA+PiArICAgICBpbnRlbF9kaXNwbGF5X3Bvd2VyX3B1 dChkZXZfcHJpdiwgUE9XRVJfRE9NQUlOX0dNQlVTKTsKPiA+PiArCj4gPj4gKyAgICAgcmV0dXJu IHJldDsKPiA+PiArfQo+ID4+ICsKPiA+PiAgc3RhdGljIHUzMiBnbWJ1c19mdW5jKHN0cnVjdCBp MmNfYWRhcHRlciAqYWRhcHRlcikKPiA+PiAgewo+ID4+ICAgICAgIHJldHVybiBpMmNfYml0X2Fs Z28uZnVuY3Rpb25hbGl0eShhZGFwdGVyKSAmCj4gPj4gLS0KPiA+PiAyLjE1LjAuNTMxLmcyY2Ni MzAxMmM5LWdvb2cKPiA+Pgo+ID4+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCj4gPj4gZHJpLWRldmVsIG1haWxpbmcgbGlzdAo+ID4+IGRyaS1kZXZlbEBs aXN0cy5mcmVlZGVza3RvcC5vcmcKPiA+PiBodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9t YWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo+ID4KPiA+IC0tCj4gPiBWaWxsZSBTeXJqw6Rsw6QK PiA+IEludGVsIE9UQwoKLS0gClZpbGxlIFN5cmrDpGzDpApJbnRlbCBPVEMKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlz dApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0 b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751468AbdLAUDo (ORCPT ); Fri, 1 Dec 2017 15:03:44 -0500 Received: from mga07.intel.com ([134.134.136.100]:36845 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750965AbdLAUDm (ORCPT ); Fri, 1 Dec 2017 15:03:42 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,346,1508828400"; d="scan'208";a="9451658" Date: Fri, 1 Dec 2017 22:03:38 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Sean Paul Cc: dri-devel , Intel Graphics Development , David Airlie , Joonas Lahtinen , Linux Kernel Mailing List , Rodrigo Vivi , Daniel Vetter Subject: Re: [PATCH v2 6/8] drm/i915: Add function to output Aksv over GMBUS Message-ID: <20171201200338.GN10981@intel.com> References: <20171201172032.47357-1-seanpaul@chromium.org> <20171201172032.47357-7-seanpaul@chromium.org> <20171201190614.GM10981@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.7.2 (2016-11-26) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 01, 2017 at 02:17:19PM -0500, Sean Paul wrote: > On Fri, Dec 1, 2017 at 2:06 PM, Ville Syrjälä > wrote: > > On Fri, Dec 01, 2017 at 12:20:28PM -0500, Sean Paul wrote: > >> Once the Aksv is available in the PCH, we need to get it on the wire to > >> the receiver via DDC. The hardware doesn't allow us to read the value > >> directly, so we need to tell GMBUS to source the Aksv internally and > >> send it to the right offset on the receiver. > >> > >> The way we do this is to initiate an indexed write where the index is > >> the Aksv register offset. We write dummy values to GMBUS3 as if we were > >> sending the key, and the hardware slips in the "real" values when it > >> goes out. > >> > >> Changes in v2: > >> - None > >> > >> Signed-off-by: Sean Paul > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 1 + > >> drivers/gpu/drm/i915/i915_reg.h | 1 + > >> drivers/gpu/drm/i915/intel_i2c.c | 54 ++++++++++++++++++++++++++++++++++------ > >> 3 files changed, 48 insertions(+), 8 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> index 36bb4927484a..10f740c9e571 100644 > >> --- a/drivers/gpu/drm/i915/i915_drv.h > >> +++ b/drivers/gpu/drm/i915/i915_drv.h > >> @@ -4043,6 +4043,7 @@ extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); > >> extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); > >> extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, > >> unsigned int pin); > >> +extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter); > >> > >> extern struct i2c_adapter * > >> intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index 6dca305ccbf7..8b71a20882ca 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -3040,6 +3040,7 @@ enum i915_power_well_id { > >> # define GPIO_DATA_PULLUP_DISABLE (1 << 13) > >> > >> #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ > >> +#define GMBUS_AKSV_SELECT (1<<11) > >> #define GMBUS_RATE_100KHZ (0<<8) > >> #define GMBUS_RATE_50KHZ (1<<8) > >> #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ > >> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > >> index eb5827110d8f..c01156bf0f27 100644 > >> --- a/drivers/gpu/drm/i915/intel_i2c.c > >> +++ b/drivers/gpu/drm/i915/intel_i2c.c > >> @@ -30,6 +30,7 @@ > >> #include > >> #include > >> #include > >> +#include > >> #include "intel_drv.h" > >> #include > >> #include "i915_drv.h" > >> @@ -373,7 +374,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, > >> > >> static int > >> gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > >> - unsigned short addr, u8 *buf, unsigned int len) > >> + unsigned short addr, u8 *buf, unsigned int len, > >> + u32 gmbus1_index) > >> { > >> unsigned int chunk_size = len; > >> u32 val, loop; > >> @@ -386,7 +388,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > >> > >> I915_WRITE_FW(GMBUS3, val); > >> I915_WRITE_FW(GMBUS1, > >> - GMBUS_CYCLE_WAIT | > >> + gmbus1_index | GMBUS_CYCLE_WAIT | > >> (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | > >> (addr << GMBUS_SLAVE_ADDR_SHIFT) | > >> GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); > >> @@ -409,7 +411,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > >> } > >> > >> static int > >> -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) > >> +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, > >> + u32 gmbus1_index) > >> { > >> u8 *buf = msg->buf; > >> unsigned int tx_size = msg->len; > >> @@ -419,7 +422,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) > >> do { > >> len = min(tx_size, GMBUS_BYTE_COUNT_MAX); > >> > >> - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); > >> + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, > >> + gmbus1_index); > >> if (ret) > >> return ret; > >> > >> @@ -470,7 +474,8 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) > >> } > >> > >> static int > >> -do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > >> +do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > >> + u32 gmbus0_source, u32 gmbus1_index) > >> { > >> struct intel_gmbus *bus = container_of(adapter, > >> struct intel_gmbus, > >> @@ -480,7 +485,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > >> int ret = 0; > >> > >> retry: > >> - I915_WRITE_FW(GMBUS0, bus->reg0); > >> + I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); > >> > >> for (; i < num; i += inc) { > >> inc = 1; > >> @@ -490,7 +495,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > >> } else if (msgs[i].flags & I2C_M_RD) { > >> ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); > >> } else { > >> - ret = gmbus_xfer_write(dev_priv, &msgs[i]); > >> + ret = gmbus_xfer_write(dev_priv, &msgs[i], > >> + gmbus1_index); > >> } > >> > >> if (!ret) > >> @@ -598,7 +604,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > >> if (ret < 0) > >> bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; > >> } else { > >> - ret = do_gmbus_xfer(adapter, msgs, num); > >> + ret = do_gmbus_xfer(adapter, msgs, num, 0, 0); > >> if (ret == -EAGAIN) > >> bus->force_bit |= GMBUS_FORCE_BIT_RETRY; > >> } > >> @@ -608,6 +614,38 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > >> return ret; > >> } > >> > >> +int intel_gmbus_output_aksv(struct i2c_adapter *adapter) > >> +{ > >> + struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, > >> + adapter); > >> + struct drm_i915_private *dev_priv = bus->dev_priv; > >> + int ret; > >> + u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; > >> + struct i2c_msg msg = { > >> + .addr = DRM_HDCP_DDC_ADDR, > >> + .flags = 0, > >> + .len = sizeof(buf), > >> + .buf = buf, > >> + }; > >> + > >> + intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); > >> + mutex_lock(&dev_priv->gmbus_mutex); > >> + > >> + /* > >> + * In order to output Aksv to the receiver, use an indexed write to > >> + * pass the i2c command, and tell GMBUS to use the HW-provided value > >> + * instead of sourcing GMBUS3 for the data. > >> + */ > >> + ret = do_gmbus_xfer(adapter, &msg, 1, GMBUS_AKSV_SELECT, > >> + GMBUS_CYCLE_INDEX | > >> + (DRM_HDCP_DDC_AKSV << GMBUS_SLAVE_INDEX_SHIFT)); > > > > It might be nicer to just use two msgs here and modify > > gmbus_xfer_index_read() to support indexed writes as well. > > I think two msgs implies a STOP bit in between. At least, that's how I > interpret "normal" writes. There is never a step between two msgs AIUI, unless you specify I2C_M_STOP. There might be a repeated start. If we want to be pedantic about the repeated start we could use the I2C_M_NOSTART flag. Although I don't think this stuff is really documented anywhere so I'm not sure if I2C_M_NOSTART is really supposed to apply to two messages with the same slave address and same direction, or if it's just meant to suppress the repeated start when changing the direction of the bus (which gmbus can't do, and we actually fail to check for that). I suppose i2c-algo-bit is the defacto standard here. And that one seems to do the repeated start whenever I2C_M_NOSTART is not specified. Would be actually nice to know what gmbus does when you just do two back to back non-indexed writes to the same slave address. If it doesn't do a repeated start in between, then I guess we're also violating I2C_M_NOSTART currently. > > > Would avoid having to pass in the GMBUS1 value all the way. > > We could infer an indexed write if num_msgs == 1 && flags == 0 && len > > 1. However that would require us to assume that all single msg > writes have a command byte at the beginning of the transaction, which > might not be true for all i2c slaves. > > Sean > > > > > > Not sure what to do with GMBUS_AKSV_SELECT. I guess either pass > > it in explicitly like you're doing here, or maybe add a small > > helper ala gmbus_is_index_read() so that do_gmbus_xfer() could > > sniff out which source we should use based on the passed in msgs? > > > >> + > >> + mutex_unlock(&dev_priv->gmbus_mutex); > >> + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); > >> + > >> + return ret; > >> +} > >> + > >> static u32 gmbus_func(struct i2c_adapter *adapter) > >> { > >> return i2c_bit_algo.functionality(adapter) & > >> -- > >> 2.15.0.531.g2ccb3012c9-goog > >> > >> _______________________________________________ > >> dri-devel mailing list > >> dri-devel@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > -- > > Ville Syrjälä > > Intel OTC -- Ville Syrjälä Intel OTC