From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@lunn.ch (Andrew Lunn) Date: Sun, 3 Dec 2017 04:25:31 +0100 Subject: [PATCH net-next 3/5] net: phy: realtek: group all register bit #defines for RTL821x_INER In-Reply-To: <20171202215128.20202-4-martin.blumenstingl@googlemail.com> References: <20171202215128.20202-1-martin.blumenstingl@googlemail.com> <20171202215128.20202-4-martin.blumenstingl@googlemail.com> Message-ID: <20171203032531.GC21613@lunn.ch> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On Sat, Dec 02, 2017 at 10:51:26PM +0100, Martin Blumenstingl wrote: > This simply moves all register bit #defines which describe the (PHY > specific) bits in the RTL821x_INER right below the RTL821x_INER register > definition. This makes it easier to spot which registers and bits belong > together. > No functional changes. > > Signed-off-by: Martin Blumenstingl Reviewed-by: Andrew Lunn Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH net-next 3/5] net: phy: realtek: group all register bit #defines for RTL821x_INER Date: Sun, 3 Dec 2017 04:25:31 +0100 Message-ID: <20171203032531.GC21613@lunn.ch> References: <20171202215128.20202-1-martin.blumenstingl@googlemail.com> <20171202215128.20202-4-martin.blumenstingl@googlemail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: netdev@vger.kernel.org, f.fainelli@gmail.com, linux-amlogic@lists.infradead.org, hkallweit1@gmail.com, Shengzhou.Liu@freescale.com, jaswinder.singh@linaro.org To: Martin Blumenstingl Return-path: Received: from vps0.lunn.ch ([185.16.172.187]:44492 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752139AbdLCDZd (ORCPT ); Sat, 2 Dec 2017 22:25:33 -0500 Content-Disposition: inline In-Reply-To: <20171202215128.20202-4-martin.blumenstingl@googlemail.com> Sender: netdev-owner@vger.kernel.org List-ID: On Sat, Dec 02, 2017 at 10:51:26PM +0100, Martin Blumenstingl wrote: > This simply moves all register bit #defines which describe the (PHY > specific) bits in the RTL821x_INER right below the RTL821x_INER register > definition. This makes it easier to spot which registers and bits belong > together. > No functional changes. > > Signed-off-by: Martin Blumenstingl Reviewed-by: Andrew Lunn Andrew