Re: [PATCH v2 01/17] xen: x86: expose SGX to HVM domain in CPU featureset

[Boqun Feng <boqun.feng@intel.com>]

On Mon, Dec 04, 2017 at 11:13:45AM +0000, Julien Grall wrote:
> Hello,
> 

Hi Julien,

> I am not sure to understand why I am being CCed. But it looks like you CC
> everyone on each patch... Please CC only relevant person on each patch.
> 

Apologies...  I thought the whole pathset will provide more context for
the reviewers. Will drop you from unrelevant patches in next verion. And
I guess it's OK for me to drop you from replies on unrelevant patches of
this version too?

Regards,
Boqun

> Cheers,
> 
> On 04/12/17 00:15, Boqun Feng wrote:
> > From: Kai Huang <kai.huang@linux.intel.com>
> > 
> > Expose SGX in CPU featureset for HVM domain. SGX will not be supported for
> > PV domain, as ENCLS (which SGX driver in guest essentially runs) must run
> > in ring 0, while PV kernel runs in ring 3. Theoretically we can support SGX
> > in PV domain via either emulating #GP caused by ENCLS running in ring 3, or
> > by PV ENCLS but it is really not necessary at this stage.
> > 
> > SGX Launch Control is also exposed in CPU featureset for HVM domain. SGX
> > Launch Control depends on SGX.
> > 
> > Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
> > Signed-off-by: Boqun Feng <boqun.feng@intel.com>
> > ---
> >   xen/include/public/arch-x86/cpufeatureset.h | 3 ++-
> >   xen/tools/gen-cpuid.py                      | 3 +++
> >   2 files changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
> > index be6da8eaf17c..1f8510eebb1d 100644
> > --- a/xen/include/public/arch-x86/cpufeatureset.h
> > +++ b/xen/include/public/arch-x86/cpufeatureset.h
> > @@ -193,7 +193,7 @@ XEN_CPUFEATURE(XSAVES,        4*32+ 3) /*S  XSAVES/XRSTORS instructions */
> >   /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
> >   XEN_CPUFEATURE(FSGSBASE,      5*32+ 0) /*A  {RD,WR}{FS,GS}BASE instructions */
> >   XEN_CPUFEATURE(TSC_ADJUST,    5*32+ 1) /*S  TSC_ADJUST MSR available */
> > -XEN_CPUFEATURE(SGX,           5*32+ 2) /*   Software Guard extensions */
> > +XEN_CPUFEATURE(SGX,           5*32+ 2) /*H  Intel Software Guard extensions */
> >   XEN_CPUFEATURE(BMI1,          5*32+ 3) /*A  1st bit manipulation extensions */
> >   XEN_CPUFEATURE(HLE,           5*32+ 4) /*A  Hardware Lock Elision */
> >   XEN_CPUFEATURE(AVX2,          5*32+ 5) /*A  AVX2 instructions */
> > @@ -230,6 +230,7 @@ XEN_CPUFEATURE(PKU,           6*32+ 3) /*H  Protection Keys for Userspace */
> >   XEN_CPUFEATURE(OSPKE,         6*32+ 4) /*!  OS Protection Keys Enable */
> >   XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A  POPCNT for vectors of DW/QW */
> >   XEN_CPUFEATURE(RDPID,         6*32+22) /*A  RDPID instruction */
> > +XEN_CPUFEATURE(SGX_LC,        6*32+30) /*H Intel SGX Launch Control */
> >   /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
> >   XEN_CPUFEATURE(ITSC,          7*32+ 8) /*   Invariant TSC */
> > diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
> > index 9ec4486f2b4b..4fef21203086 100755
> > --- a/xen/tools/gen-cpuid.py
> > +++ b/xen/tools/gen-cpuid.py
> > @@ -256,6 +256,9 @@ def crunch_numbers(state):
> >           AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
> >                     AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
> >                     AVX512_4FMAPS, AVX512_VPOPCNTDQ],
> > +
> > +        # SGX Launch Control depends on SGX
> > +        SGX: [SGX_LC],
> >       }
> >       deep_features = tuple(sorted(deps.keys()))
> > 
> 
> -- 
> Julien Grall

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