From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 6/9] drm/i915: Make use of indexed write GMBUS feature Date: Tue, 5 Dec 2017 19:33:14 +0200 Message-ID: <20171205173313.GX10981@intel.com> References: <20171205051513.8603-1-seanpaul@chromium.org> <20171205051513.8603-7-seanpaul@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20171205051513.8603-7-seanpaul@chromium.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Sean Paul Cc: seanpaul@google.com, David Airlie , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi , daniel.vetter@intel.com List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBEZWMgMDUsIDIwMTcgYXQgMTI6MTU6MDVBTSAtMDUwMCwgU2VhbiBQYXVsIHdyb3Rl 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mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751062AbdLERdS (ORCPT ); Tue, 5 Dec 2017 12:33:18 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,364,1508828400"; d="scan'208";a="9324715" Date: Tue, 5 Dec 2017 19:33:14 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Sean Paul Cc: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, seanpaul@google.com, David Airlie , linux-kernel@vger.kernel.org, Rodrigo Vivi , daniel.vetter@intel.com Subject: Re: [Intel-gfx] [PATCH v3 6/9] drm/i915: Make use of indexed write GMBUS feature Message-ID: <20171205173313.GX10981@intel.com> References: <20171205051513.8603-1-seanpaul@chromium.org> <20171205051513.8603-7-seanpaul@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20171205051513.8603-7-seanpaul@chromium.org> User-Agent: Mutt/1.7.2 (2016-11-26) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 05, 2017 at 12:15:05AM -0500, Sean Paul wrote: > This patch enables the indexed write feature of the GMBUS to concatenate > 2 consecutive messages into one. The criteria for an indexed write is > that both messages are writes, the first is length == 1, and the second > is length > 0. The first message is sent out by the GMBUS as the slave > command, and the second one is sent via the GMBUS FIFO as usual. > > Changes in v3: > - Added to series > > Suggested-by: Ville Syrjälä > Signed-off-by: Sean Paul > --- > drivers/gpu/drm/i915/intel_i2c.c | 39 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 34 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index 49fdf09f9919..7399009aee0a 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, > > static int > gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > - unsigned short addr, u8 *buf, unsigned int len) > + unsigned short addr, u8 *buf, unsigned int len, > + u32 gmbus1_index) > { > unsigned int chunk_size = len; > u32 val, loop; > @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > > I915_WRITE_FW(GMBUS3, val); > I915_WRITE_FW(GMBUS1, > - GMBUS_CYCLE_WAIT | > + gmbus1_index | GMBUS_CYCLE_WAIT | > (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | > (addr << GMBUS_SLAVE_ADDR_SHIFT) | > GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); > @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > } > > static int > -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) > +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, > + u32 gmbus1_index) > { > u8 *buf = msg->buf; > unsigned int tx_size = msg->len; > @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) > do { > len = min(tx_size, GMBUS_BYTE_COUNT_MAX); > > - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); > + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, > + gmbus1_index); > if (ret) > return ret; > > @@ -430,6 +433,14 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) > return 0; > } > > +static int > +gmbus_xfer_index_write(struct drm_i915_private *dev_priv, u8 cmd, > + struct i2c_msg *msg) > +{ > + u8 gmbus1_index = GMBUS_CYCLE_INDEX | (cmd << GMBUS_SLAVE_INDEX_SHIFT); > + return gmbus_xfer_write(dev_priv, msg, gmbus1_index); > +} Instead of a duplicating the entire thing I'd just - gmbus_xfer_index_read + gmbus_xfer_index { ... + if (msgs[1].flags & I2C_M_RD) gmbus_xfer_read() + else + gmbus_xfer_write() ... } Matches the current pattern better (no 'cmd' passed in), and will give us the 2 byte index for free as well. > + > /* > * The gmbus controller can combine a 1 or 2 byte write with a read that > * immediately follows it by using an "INDEX" cycle. > @@ -444,6 +455,20 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) > (msgs[i + 1].flags & I2C_M_RD)); > } > > +/* > + * The gmbus controller can combine a 2-msg write into a single write that > + * immediately follows it by using an "INDEX" cycle. > + */ > +static bool > +gmbus_is_index_write(struct i2c_msg *msgs, int i, int num) > +{ > + return (i + 1 < num && > + msgs[i].addr == msgs[i + 1].addr && > + !(msgs[i].flags & I2C_M_RD) && > + !(msgs[i + 1].flags & I2C_M_RD) && > + (msgs[i].len == 1 || msgs[i + 1].len > 0)); Hmm. We don't have the len check for the second msg for reads. I wonder if gmbus can actually do a zero length "read/write"? > +} > + > static int > gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) > { > @@ -489,10 +514,14 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) > if (gmbus_is_index_read(msgs, i, num)) { > ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); > inc = 2; /* an index read is two msgs */ > + } else if (gmbus_is_index_write(msgs, i, num)) { > + ret = gmbus_xfer_index_write(dev_priv, msgs[i].buf[0], > + &msgs[i + 1]); > + inc = 2; /* an index write is two msgs */ > } else if (msgs[i].flags & I2C_M_RD) { > ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); > } else { > - ret = gmbus_xfer_write(dev_priv, &msgs[i]); > + ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); > } > > if (!ret) > -- > 2.15.0.531.g2ccb3012c9-goog > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC