From: Stephen Boyd <sboyd@codeaurora.org>
To: Abhishek Sahu <absahu@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties
Date: Fri, 8 Dec 2017 16:18:51 -0800 [thread overview]
Message-ID: <20171209001851.GJ7997@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-6-git-send-email-absahu@codeaurora.org>
On 09/28, Abhishek Sahu wrote:
> Currently SUPPORTS_16BIT_ALPHA flag determines the PLL alpha
> register width. If this flag is set then the alpha register width
> is 16 bits otherwise it is 40 bits. The alpha width is always
> fixed for PLL type so it can be added in PLL properties and clock
> driver don’t have to specify explicitly.
>
> The SUPPORTS_16BIT_ALPHA flag is unused in the current code so
> it’s safe to remove this flags.
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-12-09 0:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset Abhishek Sahu
2017-09-28 17:50 ` [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Abhishek Sahu
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd [this message]
2017-09-28 17:50 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-12-07 6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55 ` Abhishek Sahu
2017-12-09 0:16 ` Stephen Boyd
2017-12-11 6:26 ` Abhishek Sahu
2017-12-13 22:23 ` Stephen Boyd
2017-12-14 5:48 ` Abhishek Sahu
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