From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOZWP-0008SS-HO for qemu-devel@nongnu.org; Mon, 11 Dec 2017 20:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eOZWL-0004IB-KE for qemu-devel@nongnu.org; Mon, 11 Dec 2017 20:38:13 -0500 Received: from mga06.intel.com ([134.134.136.31]:28783) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eOZWL-0004H9-As for qemu-devel@nongnu.org; Mon, 11 Dec 2017 20:38:09 -0500 Date: Tue, 12 Dec 2017 02:35:16 +0800 From: Chao Gao Message-ID: <20171211183516.GB18476@op-computing> References: <1510899865-40323-1-git-send-email-chao.gao@intel.com> <1510899865-40323-4-git-send-email-chao.gao@intel.com> <20171211180748.GD2216@perard.uk.xensource.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171211180748.GD2216@perard.uk.xensource.com> Subject: Re: [Qemu-devel] [PATCH v3 3/3] msi: Handle remappable format interrupt request List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony PERARD Cc: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org, Marcel Apfelbaum , Eduardo Habkost , Richard Henderson , Paolo Bonzini , "Michael S. Tsirkin" , Stefano Stabellini , Lan Tianyu On Mon, Dec 11, 2017 at 06:07:48PM +0000, Anthony PERARD wrote: >On Fri, Nov 17, 2017 at 02:24:25PM +0800, Chao Gao wrote: >> According to VT-d spec Interrupt Remapping and Interrupt Posting -> >> Interrupt Remapping -> Interrupt Request Formats On Intel 64 >> Platforms, fields of MSI data register have changed. This patch >> avoids wrongly regarding a remappable format interrupt request as >> an interrupt binded with a pirq. >> >> Signed-off-by: Chao Gao >> Signed-off-by: Lan Tianyu >> --- >> v3: >> - clarify the interrupt format bit is Intel-specific, then it is >> improper to define MSI_ADDR_IF_MASK in a common header. >> --- >> hw/i386/xen/xen-hvm.c | 10 +++++++++- >> hw/pci/msi.c | 5 +++-- >> hw/pci/msix.c | 4 +++- >> hw/xen/xen_pt_msi.c | 2 +- >> include/hw/xen/xen.h | 2 +- >> stubs/xen-hvm.c | 2 +- >> 6 files changed, 18 insertions(+), 7 deletions(-) >> >> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c >> index 8028bed..52dc8af 100644 >> --- a/hw/i386/xen/xen-hvm.c >> +++ b/hw/i386/xen/xen-hvm.c >> @@ -145,8 +145,16 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len) >> } >> } >> >> -int xen_is_pirq_msi(uint32_t msi_data) >> +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data) >> { >> + /* If the MSI address is configured in remapping format, the MSI will not >> + * be remapped into a pirq. This 'if' test excludes Intel-specific >> + * remappable msi. >> + */ >> +#define MSI_ADDR_IF_MASK 0x00000010 > >I don't think that is the right place for a define, they also exist >outside of the context of the function. yes. >That define would be better at the top of this file, I think.(There is will do. Thanks Chao >probably a better place in the common headers, but I'm not sure were.) From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chao Gao Subject: Re: [PATCH v3 3/3] msi: Handle remappable format interrupt request Date: Tue, 12 Dec 2017 02:35:16 +0800 Message-ID: <20171211183516.GB18476@op-computing> References: <1510899865-40323-1-git-send-email-chao.gao@intel.com> <1510899865-40323-4-git-send-email-chao.gao@intel.com> <20171211180748.GD2216@perard.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eOZWQ-0007Ry-MO for xen-devel@lists.xenproject.org; Tue, 12 Dec 2017 01:38:14 +0000 Content-Disposition: inline In-Reply-To: <20171211180748.GD2216@perard.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: Anthony PERARD Cc: Lan Tianyu , Stefano Stabellini , Eduardo Habkost , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , xen-devel@lists.xenproject.org, Richard Henderson List-Id: xen-devel@lists.xenproject.org T24gTW9uLCBEZWMgMTEsIDIwMTcgYXQgMDY6MDc6NDhQTSArMDAwMCwgQW50aG9ueSBQRVJBUkQg d3JvdGU6Cj5PbiBGcmksIE5vdiAxNywgMjAxNyBhdCAwMjoyNDoyNVBNICswODAwLCBDaGFvIEdh byB3cm90ZToKPj4gQWNjb3JkaW5nIHRvIFZULWQgc3BlYyBJbnRlcnJ1cHQgUmVtYXBwaW5nIGFu ZCBJbnRlcnJ1cHQgUG9zdGluZyAtPgo+PiBJbnRlcnJ1cHQgUmVtYXBwaW5nIC0+IEludGVycnVw dCBSZXF1ZXN0IEZvcm1hdHMgT24gSW50ZWwgNjQKPj4gUGxhdGZvcm1zLCBmaWVsZHMgb2YgTVNJ IGRhdGEgcmVnaXN0ZXIgaGF2ZSBjaGFuZ2VkLiBUaGlzIHBhdGNoCj4+IGF2b2lkcyB3cm9uZ2x5 IHJlZ2FyZGluZyBhIHJlbWFwcGFibGUgZm9ybWF0IGludGVycnVwdCByZXF1ZXN0IGFzCj4+IGFu IGludGVycnVwdCBiaW5kZWQgd2l0aCBhIHBpcnEuCj4+IAo+PiBTaWduZWQtb2ZmLWJ5OiBDaGFv IEdhbyA8Y2hhby5nYW9AaW50ZWwuY29tPgo+PiBTaWduZWQtb2ZmLWJ5OiBMYW4gVGlhbnl1IDx0 aWFueXUubGFuQGludGVsLmNvbT4KPj4gLS0tCj4+IHYzOgo+PiAgLSBjbGFyaWZ5IHRoZSBpbnRl cnJ1cHQgZm9ybWF0IGJpdCBpcyBJbnRlbC1zcGVjaWZpYywgdGhlbiBpdCBpcwo+PiAgaW1wcm9w ZXIgdG8gZGVmaW5lIE1TSV9BRERSX0lGX01BU0sgaW4gYSBjb21tb24gaGVhZGVyLgo+PiAtLS0K Pj4gIGh3L2kzODYveGVuL3hlbi1odm0uYyB8IDEwICsrKysrKysrKy0KPj4gIGh3L3BjaS9tc2ku YyAgICAgICAgICB8ICA1ICsrKy0tCj4+ICBody9wY2kvbXNpeC5jICAgICAgICAgfCAgNCArKyst Cj4+ICBody94ZW4veGVuX3B0X21zaS5jICAgfCAgMiArLQo+PiAgaW5jbHVkZS9ody94ZW4veGVu LmggIHwgIDIgKy0KPj4gIHN0dWJzL3hlbi1odm0uYyAgICAgICB8ICAyICstCj4+ICA2IGZpbGVz IGNoYW5nZWQsIDE4IGluc2VydGlvbnMoKyksIDcgZGVsZXRpb25zKC0pCj4+IAo+PiBkaWZmIC0t Z2l0IGEvaHcvaTM4Ni94ZW4veGVuLWh2bS5jIGIvaHcvaTM4Ni94ZW4veGVuLWh2bS5jCj4+IGlu ZGV4IDgwMjhiZWQuLjUyZGM4YWYgMTAwNjQ0Cj4+IC0tLSBhL2h3L2kzODYveGVuL3hlbi1odm0u Ywo+PiArKysgYi9ody9pMzg2L3hlbi94ZW4taHZtLmMKPj4gQEAgLTE0NSw4ICsxNDUsMTYgQEAg dm9pZCB4ZW5fcGlpeF9wY2lfd3JpdGVfY29uZmlnX2NsaWVudCh1aW50MzJfdCBhZGRyZXNzLCB1 aW50MzJfdCB2YWwsIGludCBsZW4pCj4+ICAgICAgfQo+PiAgfQo+PiAgCj4+IC1pbnQgeGVuX2lz X3BpcnFfbXNpKHVpbnQzMl90IG1zaV9kYXRhKQo+PiAraW50IHhlbl9pc19waXJxX21zaSh1aW50 MzJfdCBtc2lfYWRkcl9sbywgdWludDMyX3QgbXNpX2RhdGEpCj4+ICB7Cj4+ICsgICAgLyogSWYg dGhlIE1TSSBhZGRyZXNzIGlzIGNvbmZpZ3VyZWQgaW4gcmVtYXBwaW5nIGZvcm1hdCwgdGhlIE1T SSB3aWxsIG5vdAo+PiArICAgICAqIGJlIHJlbWFwcGVkIGludG8gYSBwaXJxLiBUaGlzICdpZicg dGVzdCBleGNsdWRlcyBJbnRlbC1zcGVjaWZpYwo+PiArICAgICAqIHJlbWFwcGFibGUgbXNpLgo+ PiArICAgICAqLwo+PiArI2RlZmluZSBNU0lfQUREUl9JRl9NQVNLIDB4MDAwMDAwMTAKPgo+SSBk b24ndCB0aGluayB0aGF0IGlzIHRoZSByaWdodCBwbGFjZSBmb3IgYSBkZWZpbmUsIHRoZXkgYWxz byBleGlzdAo+b3V0c2lkZSBvZiB0aGUgY29udGV4dCBvZiB0aGUgZnVuY3Rpb24uCgp5ZXMuCgo+ VGhhdCBkZWZpbmUgd291bGQgYmUgYmV0dGVyIGF0IHRoZSB0b3Agb2YgdGhpcyBmaWxlLCBJIHRo aW5rLihUaGVyZSBpcwoKd2lsbCBkby4KClRoYW5rcwpDaGFvCgo+cHJvYmFibHkgYSBiZXR0ZXIg cGxhY2UgaW4gdGhlIGNvbW1vbiBoZWFkZXJzLCBidXQgSSdtIG5vdCBzdXJlIHdlcmUuKQoKCl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fClhlbi1kZXZlbCBt YWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhlbnByb2plY3Qub3JnCmh0dHBzOi8vbGlzdHMu eGVucHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby94ZW4tZGV2ZWw=