From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 From: Vinod Koul Message-Id: <20171222121817.GV18649@localhost> Date: Fri, 22 Dec 2017 17:48:17 +0530 To: Peter Ujfalusi Cc: linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vigneshr@ti.com, linux-omap@vger.kernel.org List-ID: T24gVHVlLCBEZWMgMTksIDIwMTcgYXQgMTI6NTE6MTZQTSArMDIwMCwgUGV0ZXIgVWpmYWx1c2kg d3JvdGU6Cj4gRnJvbTogVmlnbmVzaCBSIDx2aWduZXNockB0aS5jb20+Cj4gCj4gUmVnaXN0ZXIg bGF5b3V0IG9mIGEgdHlwaWNhbCBUUENDX0VWVF9NVVhfTV9OIHJlZ2lzdGVyIGlzIHN1Y2ggdGhh dCB0aGUKPiBsb3dlc3QgbnVtYmVyZWQgZXZlbnQgaXMgYXQgdGhlIGxvd2VzdCBieXRlIGFkZHJl c3MgYW5kIGhpZ2hlc3QgbnVtYmVyZWQKPiBldmVudCBhdCBoaWdoZXN0IGJ5dGUgYWRkcmVzcy4g QnV0IFRQQ0NfRVZUX01VWF82MF82MyByZWdpc3RlciBsYXlvdXQgaXMKPiBkaWZmZXJlbnQsICBp biB0aGF0IHRoZSBsb3dlc3QgbnVtYmVyZWQgZXZlbnQgaXMgYXQgdGhlIGhpZ2hlc3QgYWRkcmVz cwo+IGFuZCBoaWdoZXN0IG51bWJlcmVkIGV2ZW50IGlzIGF0IHRoZSBsb3dlc3QgYWRkcmVzcy4g VGhlcmVmb3JlLCBtb2RpZnkKPiB0aV9hbTMzNXhfeGJhcl93cml0ZSgpIHRvIGhhbmRsZSBUUEND X0VWVF9NVVhfNjBfNjMgcmVnaXN0ZXIKPiBhY2NvcmRpbmdseS4KCkFwcGxpZWQsIHRoYW5rcwo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Subject: Re: [PATCH] dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 Date: Fri, 22 Dec 2017 17:48:17 +0530 Message-ID: <20171222121817.GV18649@localhost> References: <20171219105116.24335-1-peter.ujfalusi@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20171219105116.24335-1-peter.ujfalusi@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Peter Ujfalusi Cc: dmaengine@vger.kernel.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vigneshr@ti.com List-Id: linux-omap@vger.kernel.org On Tue, Dec 19, 2017 at 12:51:16PM +0200, Peter Ujfalusi wrote: > From: Vignesh R > > Register layout of a typical TPCC_EVT_MUX_M_N register is such that the > lowest numbered event is at the lowest byte address and highest numbered > event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is > different, in that the lowest numbered event is at the highest address > and highest numbered event is at the lowest address. Therefore, modify > ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register > accordingly. Applied, thanks -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Fri, 22 Dec 2017 17:48:17 +0530 Subject: [PATCH] dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 In-Reply-To: <20171219105116.24335-1-peter.ujfalusi@ti.com> References: <20171219105116.24335-1-peter.ujfalusi@ti.com> Message-ID: <20171222121817.GV18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Dec 19, 2017 at 12:51:16PM +0200, Peter Ujfalusi wrote: > From: Vignesh R > > Register layout of a typical TPCC_EVT_MUX_M_N register is such that the > lowest numbered event is at the lowest byte address and highest numbered > event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is > different, in that the lowest numbered event is at the highest address > and highest numbered event is at the lowest address. Therefore, modify > ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register > accordingly. Applied, thanks -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756735AbdLVMO2 (ORCPT ); Fri, 22 Dec 2017 07:14:28 -0500 Received: from mga04.intel.com ([192.55.52.120]:41496 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756131AbdLVMOW (ORCPT ); Fri, 22 Dec 2017 07:14:22 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,440,1508828400"; d="scan'208";a="14825250" Date: Fri, 22 Dec 2017 17:48:17 +0530 From: Vinod Koul To: Peter Ujfalusi Cc: linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vigneshr@ti.com, linux-omap@vger.kernel.org Subject: Re: [PATCH] dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 Message-ID: <20171222121817.GV18649@localhost> References: <20171219105116.24335-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171219105116.24335-1-peter.ujfalusi@ti.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 19, 2017 at 12:51:16PM +0200, Peter Ujfalusi wrote: > From: Vignesh R > > Register layout of a typical TPCC_EVT_MUX_M_N register is such that the > lowest numbered event is at the lowest byte address and highest numbered > event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is > different, in that the lowest numbered event is at the highest address > and highest numbered event is at the lowest address. Therefore, modify > ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register > accordingly. Applied, thanks -- ~Vinod