diff for duplicates of <20171229001417.GC7997@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index d0fa7ea..1512006 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,16 +3,16 @@ On 12/28, Alexander Kochetkov wrote: > https://www.spinics.net/lists/linux-clk/msg21682.html > > -> > 27 дек. 2017 г., в 4:06, Stephen Boyd <sboyd@codeaurora.org> написал(а): +> > 27 ???. 2017 ?., ? 4:06, Stephen Boyd <sboyd@codeaurora.org> ???????(?): > > > > Are these limits the min/max limits that the parent clk can > > output at? Or the min/max limits that software has constrained on > > the clk? > > > -> Don’t know how to answer. For example, parent can output 768MHz, +> Don?t know how to answer. For example, parent can output 768MHz, > but some IP work unstable with that parent rate. This issues was observed by -> me and I didn’t get official confirmation from rockchip. So, I limit +> me and I didn?t get official confirmation from rockchip. So, I limit > such clock to 192MHz using clk_set_max_rate(). May be I have to limit clk rate > using another approach. @@ -45,7 +45,7 @@ express a hardware constraint. > I limit i2s0_pre rate to 192MHz in order to I2S IP work properly. > rockchip_fractional_approximation() get called for i2s0_frac. > if i2s0_pre rate is 20x times less than i2s0_frac, than rockchip_fractional_approximation() -> tries to set i2s0_pre rate to i2s_src rate. It tries to increase it’s parent rate in order +> tries to set i2s0_pre rate to i2s_src rate. It tries to increase it?s parent rate in order > to maximise relation between nominator and denominator. > > If I convert rockchip_fractional_approximation() to rockchip_determine_rate(), than I get @@ -56,7 +56,7 @@ express a hardware constraint. > Also found, that rockchip_fractional_approximation() increase parents rate unconditionally > without taking into account CLK_SET_RATE_PARENT flag. > -> Stephen, thanks a lot for deep description of determine_rate() background. I’ll taking some +> Stephen, thanks a lot for deep description of determine_rate() background. I?ll taking some > time thinking about possible solutions. > diff --git a/a/content_digest b/N1/content_digest index 1de1b2b..f447972 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,17 +4,10 @@ "ref\08EC4D15B-4A89-43FA-953E-95AF81417067@gmail.com\0" "ref\020171227010638.GP7997@codeaurora.org\0" "ref\04B1BB338-F1F9-4231-BDCA-5FBB1F61BC44@gmail.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" - "Subject\0Re: [PATCH 1/2] clk: rename clk_core_get_boundaries() to clk_hw_get_boundaries() and expose\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" + "Subject\0[PATCH 1/2] clk: rename clk_core_get_boundaries() to clk_hw_get_boundaries() and expose\0" "Date\0Thu, 28 Dec 2017 16:14:17 -0800\0" - "To\0Alexander Kochetkov <al.kochet@gmail.com>\0" - "Cc\0linux-clk@vger.kernel.org" - LKML <linux-kernel@vger.kernel.org> - LAK <linux-arm-kernel@lists.infradead.org> - linux-rockchip@lists.infradead.org - Michael Turquette <mturquette@baylibre.com> - Heiko Stuebner <heiko@sntech.de> - " Elaine Zhang <zhangqing@rock-chips.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 12/28, Alexander Kochetkov wrote:\n" @@ -22,16 +15,16 @@ "> https://www.spinics.net/lists/linux-clk/msg21682.html\n" "> \n" "> \n" - "> > 27 \320\264\320\265\320\272. 2017 \320\263., \320\262 4:06, Stephen Boyd <sboyd@codeaurora.org> \320\275\320\260\320\277\320\270\321\201\320\260\320\273(\320\260):\n" + "> > 27 ???. 2017 ?., ? 4:06, Stephen Boyd <sboyd@codeaurora.org> ???????(?):\n" "> > \n" "> > Are these limits the min/max limits that the parent clk can\n" "> > output at? Or the min/max limits that software has constrained on\n" "> > the clk?\n" "> > \n" "> \n" - "> Don\342\200\231t know how to answer. For example, parent can output 768MHz,\n" + "> Don?t know how to answer. For example, parent can output 768MHz,\n" "> but some IP work unstable with that parent rate. This issues was observed by\n" - "> me and I didn\342\200\231t get official confirmation from rockchip. So, I limit\n" + "> me and I didn?t get official confirmation from rockchip. So, I limit\n" "> such clock to 192MHz using clk_set_max_rate(). May be I have to limit clk rate\n" "> using another approach.\n" "\n" @@ -64,7 +57,7 @@ "> I limit i2s0_pre rate to 192MHz in order to I2S IP work properly.\n" "> rockchip_fractional_approximation() get called for i2s0_frac.\n" "> if i2s0_pre rate is 20x times less than i2s0_frac, than rockchip_fractional_approximation()\n" - "> tries to set i2s0_pre rate to i2s_src rate. It tries to increase it\342\200\231s parent rate in order\n" + "> tries to set i2s0_pre rate to i2s_src rate. It tries to increase it?s parent rate in order\n" "> to maximise relation between nominator and denominator.\n" "> \n" "> If I convert rockchip_fractional_approximation() to rockchip_determine_rate(), than I get\n" @@ -75,7 +68,7 @@ "> Also found, that rockchip_fractional_approximation() increase parents rate unconditionally\n" "> without taking into account CLK_SET_RATE_PARENT flag.\n" "> \n" - "> Stephen, thanks a lot for deep description of determine_rate() background. I\342\200\231ll taking some\n" + "> Stephen, thanks a lot for deep description of determine_rate() background. I?ll taking some\n" "> time thinking about possible solutions.\n" "> \n" "\n" @@ -87,4 +80,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -c12c7e83ae4c939b01afc2b580082d98e2863d1a1beee1f118f2351b2ac1ee4d +cbbf3118bf23c64ade16240b666bbf0a635763249bd2851a6538012f4c293d46
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