From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yang Zhong Subject: Re: [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features Date: Thu, 4 Jan 2018 14:06:32 +0800 Message-ID: <20180104060632.GA11726@yangzhon-Virtual> References: <1514967965-9967-1-git-send-email-yang.zhong@intel.com> <1514967965-9967-5-git-send-email-yang.zhong@intel.com> <5A4CA661020000780019A5FC@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <5A4CA661020000780019A5FC@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: Jan Beulich Cc: yang.zhong@intel.com, andrew.cooper3@citrix.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org T24gV2VkLCBKYW4gMDMsIDIwMTggYXQgMDE6NDY6MDlBTSAtMDcwMCwgSmFuIEJldWxpY2ggd3Jv dGU6Cgo+ID4gLS0tIGEveGVuL2luY2x1ZGUvcHVibGljL2FyY2gteDg2L2NwdWZlYXR1cmVzZXQu aAo+ID4gKysrIGIveGVuL2luY2x1ZGUvcHVibGljL2FyY2gteDg2L2NwdWZlYXR1cmVzZXQuaAo+ ID4gQEAgLTIyOCw2ICsyMjgsMTIgQEAgWEVOX0NQVUZFQVRVUkUoQVZYNTEyVkJNSSwgICAgNioz MisgMSkgLypBICBBVlgtNTEyIFZlY3RvciBCeXRlIE1hbmlwdWxhdGlvbiBJbnMKPiA+ICBYRU5f Q1BVRkVBVFVSRShVTUlQLCAgICAgICAgICA2KjMyKyAyKSAvKlMgIFVzZXIgTW9kZSBJbnN0cnVj dGlvbiBQcmV2ZW50aW9uICovCj4gPiAgWEVOX0NQVUZFQVRVUkUoUEtVLCAgICAgICAgICAgNioz MisgMykgLypIICBQcm90ZWN0aW9uIEtleXMgZm9yIFVzZXJzcGFjZSAqLwo+ID4gIFhFTl9DUFVG RUFUVVJFKE9TUEtFLCAgICAgICAgIDYqMzIrIDQpIC8qISAgT1MgUHJvdGVjdGlvbiBLZXlzIEVu YWJsZSAqLwo+ID4gK1hFTl9DUFVGRUFUVVJFKEFWWDUxMl9WQk1JMiwgIDYqMzIrIDYpIC8qQSAg YWRkaXRpb24gQVZYLTUxMiBWQk1JIEluc3RydWN0aW9ucyAqLwo+IAo+ICJhZGRpdGlvbmFsIj8K ICBKYW4sIGkgd2lsbCBjaGFuZ2UgImFkZGl0aW9uIiB0byAiYWRkaXRpb25hbCIsIHRoYW5rcyEg WWFuZy4KIAo+ID4gLS0tIGEveGVuL3Rvb2xzL2dlbi1jcHVpZC5weQo+ID4gKysrIGIveGVuL3Rv b2xzL2dlbi1jcHVpZC5weQo+ID4gQEAgLTI1NSw3ICsyNTUsOCBAQCBkZWYgY3J1bmNoX251bWJl cnMoc3RhdGUpOgo+ID4gICAgICAgICAgIyB0b3Agb2YgQVZYNTEyRgo+ID4gICAgICAgICAgQVZY NTEyRjogW0FWWDUxMkRRLCBBVlg1MTJJRk1BLCBBVlg1MTJQRiwgQVZYNTEyRVIsIEFWWDUxMkNE LAo+ID4gICAgICAgICAgICAgICAgICAgIEFWWDUxMkJXLCBBVlg1MTJWTCwgQVZYNTEyVkJNSSwg QVZYNTEyXzRWTk5JVywKPiA+IC0gICAgICAgICAgICAgICAgICBBVlg1MTJfNEZNQVBTLCBBVlg1 MTJfVlBPUENOVERRXSwKPiA+ICsgICAgICAgICAgICAgICAgICBBVlg1MTJfNEZNQVBTLCBBVlg1 MTJfVlBPUENOVERRLCBBVlg1MTJfVkJNSTIsCj4gPiArICAgICAgICAgICAgICAgICAgQVZYNTEy X1ZOTkksIEFWWDUxMl9CSVRBTEddLAo+ID4gICAgICB9Cj4gCj4gVGhpcyBpcyBpbnN1ZmZpY2ll bnQgYWZhaWN0OiBWQUVTIGFuZCBWUENMTVVMUURRIG91Z2h0IHRvIGJlCj4gbWFkZSBkZXBlbmRl bnQgdXBvbiBBVlguCgogIFRoYW5rcyBKYW4sIGkgd2lsbCBkbyBiZWxvdyBjaGFuZ2VzIGZvciB0 aGlzLiAgWWFuZy4KCi0gICAgICAgIEFWWDogW0ZNQSwgRk1BNCwgRjE2QywgQVZYMiwgWE9QXSwK KyAgICAgICAgQVZYOiBbRk1BLCBGTUE0LCBGMTZDLCBBVlgyLCBYT1AsIFZBRVMsIFZQQ0xNVUxR RFFdLAoKPiAKPiBKYW4KCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhlbnByb2plY3Qu b3JnCmh0dHBzOi8vbGlzdHMueGVucHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby94ZW4tZGV2 ZWw=