From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Brunet Subject: [PATCH 2/5] clk: lpc32xx: read-only divider can propagate rate change Date: Fri, 5 Jan 2018 18:09:56 +0100 Message-ID: <20180105170959.17266-3-jbrunet@baylibre.com> References: <20180105170959.17266-1-jbrunet@baylibre.com> Return-path: Received: from mail-wr0-f196.google.com ([209.85.128.196]:35229 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752347AbeAERKH (ORCPT ); Fri, 5 Jan 2018 12:10:07 -0500 Received: by mail-wr0-f196.google.com with SMTP id l19so4887148wrc.2 for ; Fri, 05 Jan 2018 09:10:06 -0800 (PST) In-Reply-To: <20180105170959.17266-1-jbrunet@baylibre.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org Cc: Jerome Brunet , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Sylvain Lemieux , Andy Gross , David Brown When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the register shall be left un-touched, but it does not mean the clock should stop rate propagation if CLK_SET_RATE_PARENT is set This properly handled in qcom clk-regmap-divider but it was not in the lpc32xx divider Fixes: f7c82a60ba26 ("clk: lpc32xx: add common clock framework driver") Signed-off-by: Jerome Brunet --- drivers/clk/nxp/clk-lpc32xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index f5d815f577e0..729333766f97 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -963,6 +963,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); unsigned int bestdiv; /* if read only, just return current value */ @@ -972,6 +973,15 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, bestdiv &= div_mask(divider->width); bestdiv = _get_div(divider->table, bestdiv, divider->flags, divider->width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!hw_parent) + return -EINVAL; + + *prate = clk_hw_round_rate(hw_parent, rate * bestdiv); + } + return DIV_ROUND_UP(*prate, bestdiv); } -- 2.14.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: jbrunet@baylibre.com (Jerome Brunet) Date: Fri, 5 Jan 2018 18:09:56 +0100 Subject: [PATCH 2/5] clk: lpc32xx: read-only divider can propagate rate change In-Reply-To: <20180105170959.17266-1-jbrunet@baylibre.com> References: <20180105170959.17266-1-jbrunet@baylibre.com> Message-ID: <20180105170959.17266-3-jbrunet@baylibre.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the register shall be left un-touched, but it does not mean the clock should stop rate propagation if CLK_SET_RATE_PARENT is set This properly handled in qcom clk-regmap-divider but it was not in the lpc32xx divider Fixes: f7c82a60ba26 ("clk: lpc32xx: add common clock framework driver") Signed-off-by: Jerome Brunet --- drivers/clk/nxp/clk-lpc32xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index f5d815f577e0..729333766f97 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -963,6 +963,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); unsigned int bestdiv; /* if read only, just return current value */ @@ -972,6 +973,15 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, bestdiv &= div_mask(divider->width); bestdiv = _get_div(divider->table, bestdiv, divider->flags, divider->width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!hw_parent) + return -EINVAL; + + *prate = clk_hw_round_rate(hw_parent, rate * bestdiv); + } + return DIV_ROUND_UP(*prate, bestdiv); } -- 2.14.3