From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. Date: Fri, 5 Jan 2018 09:49:13 -0800 Message-ID: <20180105174913.t4mwhrcd5k5iazca@intel.com> References: <20180105085905.9298-1-kenneth@whitecape.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA1646E3AB for ; Fri, 5 Jan 2018 17:49:18 +0000 (UTC) Content-Disposition: inline In-Reply-To: <20180105085905.9298-1-kenneth@whitecape.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gRnJpLCBKYW4gMDUsIDIwMTggYXQgMDg6NTk6MDVBTSArMDAwMCwgS2VubmV0aCBHcmF1bmtl IHdyb3RlOgo+IEdlbWluaWxha2UgcmVxdWlyZXMgdGhlIDNEIGRyaXZlciB0byBzZWxlY3Qgd2hl dGhlciBiYXJyaWVycyBhcmUKPiBpbnRlbmRlZCBmb3IgY29tcHV0ZSBzaGFkZXJzLCBvciB0ZXNz ZWxsYXRpb24gY29udHJvbCBzaGFkZXJzLCBieQo+IHdoYWNraW5nIGEgIkJhcnJpZXIgTW9kZSIg Yml0IGluIFNMSUNFX0NPTU1PTl9FQ09fQ0hJQ0tFTjEgd2hlbgo+IHN3aXRjaGluZyBwaXBlbGlu ZXMuICBGYWlsdXJlIHRvIGRvIHRoaXMgcHJvcGVybHkgY2FuIHJlc3VsdCBpbiBHUFUKPiBoYW5n cy4KPiAKPiBVbmZvcnR1bmF0ZWx5LCB0aGlzIG1lYW5zIGl0IG5lZWRzIHRvIHN3aXRjaCBtaWQt YmF0Y2gsIHNvIG9ubHkKPiB1c2Vyc3BhY2UgY2FuIHByb3Blcmx5IHNldCBpdC4gIFRvIGZhY2ls aXRhdGUgdGhpcywgdGhlIGtlcm5lbCBuZWVkcwo+IHRvIHdoaXRlbGlzdCB0aGUgcmVnaXN0ZXIu Cj4gCj4gVGhlIHdvcmthcm91bmRzIHBhZ2UgY3VycmVudGx5IHRhZ3MgdGhpcyBhcyBhcHBseWlu ZyB0byBCcm94dG9uIG9ubHksCj4gYnV0IHRoYXQgZG9lc24ndCBtYWtlIHNlbnNlLiAgVGhlIGRv Y3VtZW50YXRpb24gZm9yIHRoZSByZWdpc3RlciBpdAo+IHJlZmVyZW5jZXMgc2F5cyB0aGUgYml0 IHVzZXJzcGFjZSBpcyBzdXBwb3NlZCB0byB0b2dnbGUgb25seSBleGlzdHMgb24KPiBHZW1pbmls YWtlLiAgRW1waXJpY2FsbHksIHRoZSBNZXNhIHBhdGNoIHRvIHRvZ2dsZSB0aGlzIGJpdCBhcHBl YXJzIHRvCj4gZml4IGludGVybWl0dGVudCBHUFUgaGFuZ3MgaW4gdGVzc2VsbGF0aW9uIGNvbnRy b2wgc2hhZGVyIGJhcnJpZXIgdGVzdHMKPiBvbiBHZW1pbmlsYWtlOyB3ZSBoYXZlbid0IHNlZW4g dGhvc2UgaGFuZ3Mgb24gQnJveHRvbi4KCkkganVzdCByZWFkIHRoZSBiaXQgZGVmaW5pdGlvbiBh bmQgZnVsbHkgYWdyZWUgd2l0aCB0aGlzLgoKPiAKPiB2MjogTWVudGlvbiBXQSAjMDg2MiBpbiB0 aGUgY29tbWVudCAoaXQgZG9lc24ndCBoYXZlIGEgbmFtZSkuCj4gCj4gU2lnbmVkLW9mZi1ieTog S2VubmV0aCBHcmF1bmtlIDxrZW5uZXRoQHdoaXRlY2FwZS5vcmc+Cj4gQWNrZWQtYnk6IFJvZHJp Z28gVml2aSA8cm9kcmlnby52aXZpQGludGVsLmNvbT4KPiBDYzogc3RhYmxlQHZnZXIua2VybmVs Lm9yZwoKTWVyZ2VkLCB0aGFua3MuCgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X3JlZy5oICAgICAgICB8IDIgKysKPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZW5naW5l X2NzLmMgfCA1ICsrKysrCj4gIDIgZmlsZXMgY2hhbmdlZCwgNyBpbnNlcnRpb25zKCspCj4gCj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmggYi9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gaW5kZXggOTY2ZTRkZjk3MDBlLi41MDVjNjA1ZWZmOTgg MTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+ICsrKyBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiBAQCAtNzA3OSw2ICs3MDc5LDggQEAgZW51 bSB7Cj4gICNkZWZpbmUgR0VOOV9TTElDRV9DT01NT05fRUNPX0NISUNLRU4wCQlfTU1JTygweDcz MDgpCj4gICNkZWZpbmUgIERJU0FCTEVfUElYRUxfTUFTS19DQU1NSU5HCQkoMTw8MTQpCj4gIAo+ ICsjZGVmaW5lIEdFTjlfU0xJQ0VfQ09NTU9OX0VDT19DSElDS0VOMQkJX01NSU8oMHg3MzFjKQo+ ICsKPiAgI2RlZmluZSBHRU43X0wzU1FDUkVHMQkJCQlfTU1JTygweEIwMTApCj4gICNkZWZpbmUg IFZMVl9CMF9XQV9MM1NRQ1JFRzFfVkFMVUUJCTB4MDBEMzAwMDAKPiAgCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2VuZ2luZV9jcy5jIGIvZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfZW5naW5lX2NzLmMKPiBpbmRleCBlYmRjYmNiYWNiM2MuLjZiYjUxYTUwMmI4 YiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9lbmdpbmVfY3MuYwo+ ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2VuZ2luZV9jcy5jCj4gQEAgLTEzMzgs NiArMTMzOCwxMSBAQCBzdGF0aWMgaW50IGdsa19pbml0X3dvcmthcm91bmRzKHN0cnVjdCBpbnRl bF9lbmdpbmVfY3MgKmVuZ2luZSkKPiAgCWlmIChyZXQpCj4gIAkJcmV0dXJuIHJldDsKPiAgCj4g KwkvKiBXQSAjMDg2MjogVXNlcnNwYWNlIGhhcyB0byBzZXQgIkJhcnJpZXIgTW9kZSIgdG8gYXZv aWQgaGFuZ3MuICovCj4gKwlyZXQgPSB3YV9yaW5nX3doaXRlbGlzdF9yZWcoZW5naW5lLCBHRU45 X1NMSUNFX0NPTU1PTl9FQ09fQ0hJQ0tFTjEpOwo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0 Owo+ICsKPiAgCS8qIFdhVG9FbmFibGVId0ZpeEZvclB1c2hDb25zdEhXQnVnOmdsayAqLwo+ICAJ V0FfU0VUX0JJVF9NQVNLRUQoQ09NTU9OX1NMSUNFX0NISUNLRU4yLAo+ICAJCQkgIEdFTjhfU0JF X0RJU0FCTEVfUkVQTEFZX0JVRl9PUFRJTUlaQVRJT04pOwo+IC0tIAo+IDIuMTUuMQo+IApfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFp bGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com ([134.134.136.24]:52554 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752493AbeAERtP (ORCPT ); Fri, 5 Jan 2018 12:49:15 -0500 Date: Fri, 5 Jan 2018 09:49:13 -0800 From: Rodrigo Vivi To: Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk, mark.a.janes@intel.com, stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. Message-ID: <20180105174913.t4mwhrcd5k5iazca@intel.com> References: <20180105085905.9298-1-kenneth@whitecape.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180105085905.9298-1-kenneth@whitecape.org> Sender: stable-owner@vger.kernel.org List-ID: On Fri, Jan 05, 2018 at 08:59:05AM +0000, Kenneth Graunke wrote: > Geminilake requires the 3D driver to select whether barriers are > intended for compute shaders, or tessellation control shaders, by > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > switching pipelines. Failure to do this properly can result in GPU > hangs. > > Unfortunately, this means it needs to switch mid-batch, so only > userspace can properly set it. To facilitate this, the kernel needs > to whitelist the register. > > The workarounds page currently tags this as applying to Broxton only, > but that doesn't make sense. The documentation for the register it > references says the bit userspace is supposed to toggle only exists on > Geminilake. Empirically, the Mesa patch to toggle this bit appears to > fix intermittent GPU hangs in tessellation control shader barrier tests > on Geminilake; we haven't seen those hangs on Broxton. I just read the bit definition and fully agree with this. > > v2: Mention WA #0862 in the comment (it doesn't have a name). > > Signed-off-by: Kenneth Graunke > Acked-by: Rodrigo Vivi > Cc: stable@vger.kernel.org Merged, thanks. > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 966e4df9700e..505c605eff98 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7079,6 +7079,8 @@ enum { > #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) > #define DISABLE_PIXEL_MASK_CAMMING (1<<14) > > +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) > + > #define GEN7_L3SQCREG1 _MMIO(0xB010) > #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index ebdcbcbacb3c..6bb51a502b8b 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > + /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ > + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1); > + if (ret) > + return ret; > + > /* WaToEnableHwFixForPushConstHWBug:glk */ > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > -- > 2.15.1 >