From: Christoph Hellwig <hch@lst.de>
To: Michael Clark <mjc@sifive.com>
Cc: qemu-devel@nongnu.org,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1
Date: Mon, 8 Jan 2018 15:24:19 +0100 [thread overview]
Message-ID: <20180108142419.GA10273@lst.de> (raw)
In-Reply-To: <1514940265-18093-1-git-send-email-mjc@sifive.com>
> The RISC-V QEMU port implements the following specifications:
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
What is the reason to support the legacy 1.9.1 privileg spec? That
support seems to make a mess of quite a lot of the code, and has been
superseded quite a while ago.
prev parent reply other threads:[~2018-01-08 14:24 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-03 0:44 [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1 Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 01/21] RISC-V Maintainers Michael Clark
2018-01-03 5:30 ` Richard Henderson
2018-01-09 21:27 ` Alistair Francis
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-03 5:30 ` Richard Henderson
2018-01-09 21:33 ` Alistair Francis
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-03 5:21 ` Richard Henderson
2018-01-03 22:30 ` Michael Clark
2018-01-08 6:55 ` Michael Clark
2018-01-04 6:47 ` Antony Pavlov
2018-01-04 7:33 ` Michael Clark
2018-01-04 17:53 ` Antony Pavlov
2018-01-05 5:59 ` Michael Clark
2018-03-03 1:41 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler Michael Clark
2018-01-03 5:30 ` Richard Henderson
2018-01-03 22:12 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers Michael Clark
2018-01-03 7:12 ` Richard Henderson
2018-01-03 22:59 ` Michael Clark
2018-01-03 23:25 ` Richard Henderson
2018-01-10 10:35 ` Stefan O'Rear
2018-01-10 17:04 ` Richard Henderson
2018-01-08 14:28 ` Christoph Hellwig
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support Michael Clark
2018-01-03 20:10 ` Richard Henderson
2018-01-23 21:37 ` Michael Clark
2018-01-24 0:01 ` Richard Henderson
2018-01-24 1:31 ` Michael Clark
2018-01-24 16:16 ` Richard Henderson
2018-01-24 17:35 ` Michael Clark
2018-01-23 23:15 ` Michael Clark
2018-01-23 23:35 ` Michael Clark
2018-01-24 0:03 ` Jim Wilson
2018-01-24 0:15 ` Richard Henderson
2018-01-24 18:58 ` Jim Wilson
2018-01-24 23:47 ` Richard Henderson
2018-01-29 20:33 ` Jim Wilson
2018-02-02 5:26 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 07/21] RISC-V GDB Stub Michael Clark
2018-01-03 20:25 ` Richard Henderson
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-03 21:35 ` Richard Henderson
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-03 23:03 ` Richard Henderson
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-03 23:47 ` Richard Henderson
2018-01-05 6:51 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console Michael Clark
2018-01-04 0:00 ` Richard Henderson
2018-01-08 14:31 ` Christoph Hellwig
2018-02-04 20:19 ` Michael Clark
2018-02-04 21:29 ` Christoph Hellwig
2018-02-04 23:23 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array Michael Clark
2018-01-04 0:08 ` Richard Henderson
2018-01-05 21:41 ` Antony Pavlov
2018-01-05 21:44 ` Eric Blake
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 15/21] RISC-V Spike Machines Michael Clark
2018-01-04 0:14 ` Richard Henderson
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-03 14:57 ` KONRAD Frederic
2018-01-05 6:38 ` Michael Clark
2018-01-04 21:07 ` Antony Pavlov
2018-01-05 6:03 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-03 15:02 ` KONRAD Frederic
2018-01-03 22:07 ` Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-05 21:54 ` Antony Pavlov
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 20/21] SiFive Freedom U500 " Michael Clark
2018-01-03 0:44 ` [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-03 23:23 ` Eric Blake
2018-01-05 6:47 ` Michael Clark
2018-01-05 14:49 ` Eric Blake
2018-01-08 9:29 ` Markus Armbruster
2018-01-04 17:09 ` Antony Pavlov
2018-01-05 6:22 ` Michael Clark
2018-02-03 22:36 ` Michael Clark
2018-01-03 1:28 ` [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1 no-reply
2018-01-03 1:46 ` Michael Clark
2018-01-03 2:00 ` Michael Clark
2018-01-03 2:41 ` Fam Zheng
2018-01-03 2:54 ` Michael Clark
2018-01-03 3:05 ` Fam Zheng
2018-01-05 11:49 ` Alex Bennée
2018-01-05 12:25 ` Fam Zheng
2018-01-05 12:39 ` Alex Bennée
2018-01-05 22:11 ` Paolo Bonzini
2018-01-03 11:35 ` Richard W.M. Jones
2018-01-03 21:50 ` Michael Clark
2018-01-03 22:06 ` Richard W.M. Jones
2018-01-08 15:45 ` Andrea Bolognani
2018-01-08 14:24 ` Christoph Hellwig [this message]
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