From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,1/4] dmaengine: xilinx_dma: populate dma caps properly From: Vinod Koul Message-Id: <20180108170655.GJ18649@localhost> Date: Mon, 8 Jan 2018 22:36:55 +0530 To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-ID: T24gTW9uLCBKYW4gMDgsIDIwMTggYXQgMTA6NTI6MDFBTSArMDAwMCwgQXBwYW5hIER1cmdhIEtl ZGFyZXN3YXJhIFJhbyB3cm90ZToKPiBIaSBWaW5vZCwKPiAKPiAJVGhhbmtzIGZvciB0aGUgcmV2 aWV3Li4uLiAKPiA8U25pcD4KPiA+PiBAQCAtMjM5OCw2ICsyMzk4LDcgQEAgc3RhdGljIGludCB4 aWxpbnhfZG1hX2NoYW5fcHJvYmUoc3RydWN0Cj4gPnhpbGlueF9kbWFfZGV2aWNlICp4ZGV2LAo+ ID4+ICAJCWNoYW4tPmRpcmVjdGlvbiA9IERNQV9NRU1fVE9fREVWOwo+ID4+ICAJCWNoYW4tPmlk ID0gY2hhbl9pZDsKPiA+PiAgCQljaGFuLT50ZGVzdCA9IGNoYW5faWQ7Cj4gPj4gKwkJeGRldi0+ Y29tbW9uLmRpcmVjdGlvbnMgPSBCSVQoRE1BX01FTV9UT19ERVYpOwo+ID4+Cj4gPj4gIAkJY2hh bi0+Y3RybF9vZmZzZXQgPSBYSUxJTlhfRE1BX01NMlNfQ1RSTF9PRkZTRVQ7Cj4gPj4gIAkJaWYg KHhkZXYtPmRtYV9jb25maWctPmRtYXR5cGUgPT0gWERNQV9UWVBFX1ZETUEpIHsgQEAgLQo+ID4y NDE1LDYKPiA+PiArMjQxNiw3IEBAIHN0YXRpYyBpbnQgeGlsaW54X2RtYV9jaGFuX3Byb2JlKHN0 cnVjdCB4aWxpbnhfZG1hX2RldmljZSAqeGRldiwKPiA+PiAgCQljaGFuLT5kaXJlY3Rpb24gPSBE TUFfREVWX1RPX01FTTsKPiA+PiAgCQljaGFuLT5pZCA9IGNoYW5faWQ7Cj4gPj4gIAkJY2hhbi0+ dGRlc3QgPSBjaGFuX2lkIC0geGRldi0+bnJfY2hhbm5lbHM7Cj4gPj4gKwkJeGRldi0+Y29tbW9u LmRpcmVjdGlvbnMgfD0gQklUKERNQV9ERVZfVE9fTUVNKTsKPiA+Pgo+ID4+ICAJCWNoYW4tPmN0 cmxfb2Zmc2V0ID0gWElMSU5YX0RNQV9TMk1NX0NUUkxfT0ZGU0VUOwo+ID4+ICAJCWlmICh4ZGV2 LT5kbWFfY29uZmlnLT5kbWF0eXBlID09IFhETUFfVFlQRV9WRE1BKSB7IEBAIC0KPiA+MjYyOSw2 Cj4gPj4gKzI2MzEsOCBAQCBzdGF0aWMgaW50IHhpbGlueF9kbWFfcHJvYmUoc3RydWN0IHBsYXRm b3JtX2RldmljZSAqcGRldikKPiA+PiAgCQlkbWFfY2FwX3NldChETUFfUFJJVkFURSwgeGRldi0+ Y29tbW9uLmNhcF9tYXNrKTsKPiA+PiAgCX0KPiA+Pgo+ID4+ICsJeGRldi0+Y29tbW9uLmRzdF9h ZGRyX3dpZHRocyA9IEJJVChhZGRyX3dpZHRoIC8gOCk7Cj4gPj4gKwl4ZGV2LT5jb21tb24uc3Jj X2FkZHJfd2lkdGhzID0gQklUKGFkZHJfd2lkdGggLyA4KTsKPiA+Cj4gPkRvIHlvdSBub3Qgc3Vw cG9ydCB0cmYgb2YgMWJ5dGUsIDIgYnl0ZXMsIG9yIDQgYnl0ZXMgd2lkZSB0cmFuc2ZlcnM/IFdo YXQgaXMgdmFsdWUKPiA+b2YgYWRkcl93aWR0aCBoZXJlIHR5cGljYWxseT8gVXN1YWxseSBjb250 cm9sbGVycyBjYW4gc3VwcG9ydCBkaWZmZXJlbnQgd2lkdGhzIGFuZAo+ID50aGlzIGlzIGEgc3Vy cHJpc2UgdGhhdCB5b3Ugc3VwcG9ydCBvbmx5IG9uZSB2YWx1ZQo+IAo+IENvbnRyb2xsZXIgc3Vw cG9ydHMgYWRkcmVzcyB3aWR0aCBvZiAzMiBhbmQgNjQuCgpUaGVuIHRoaXMgc2hvdWxkIGhhdmUg Ym90aCAzMiBhbmQgNjQgdmFsdWVzIGhlcmUKCj4gYWRkcl93aWR0aCB0eXBpY2FsIHZhbHVlcyBh cmUgMzItYml0IG9yIDY0LWJpdCAuCj4gSGVyZSBhZGRyX3dpZHRoIGlzIGRldmljZS10cmVlIHBh cmFtZXRlci4uLgo+IG15IHVuZGVyc3RhbmRpbmcgb2Ygc3JjX2FkZHJfd2lkdGhzL2RzdF9hZGRy X3dpZHRocyBpcywgaXQgaXMgYSBiaXQgbWFzayBvZiB0aGUgCj4gYWRkcmVzcyB3aXRoIGluIGJ5 dGVzIHRoYXQgRE1BIHN1cHBvcnRzLCBwbGVhc2UgY29ycmVjdCBpZiBteSB1bmRlcnN0YW5kaW5n IGlzIHdyb25nLgo+IAo+IFJlZ2FyZHMsCj4gS2VkYXIuCj4gCj4gPgo+ID4tLQo+ID5+Vmlub2QK From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Mon, 8 Jan 2018 22:36:55 +0530 Subject: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly In-Reply-To: References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> Message-ID: <20180108170655.GJ18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Jan 08, 2018 at 10:52:01AM +0000, Appana Durga Kedareswara Rao wrote: > Hi Vinod, > > Thanks for the review.... > > >> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct > >xilinx_dma_device *xdev, > >> chan->direction = DMA_MEM_TO_DEV; > >> chan->id = chan_id; > >> chan->tdest = chan_id; > >> + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > >> > >> chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2415,6 > >> +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > >> chan->direction = DMA_DEV_TO_MEM; > >> chan->id = chan_id; > >> chan->tdest = chan_id - xdev->nr_channels; > >> + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > >> > >> chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2629,6 > >> +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) > >> dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); > >> } > >> > >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > > > >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is value > >of addr_width here typically? Usually controllers can support different widths and > >this is a surprise that you support only one value > > Controller supports address width of 32 and 64. Then this should have both 32 and 64 values here > addr_width typical values are 32-bit or 64-bit . > Here addr_width is device-tree parameter... > my understanding of src_addr_widths/dst_addr_widths is, it is a bit mask of the > address with in bytes that DMA supports, please correct if my understanding is wrong. > > Regards, > Kedar. > > > > >-- > >~Vinod -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935416AbeAHRCs (ORCPT + 1 other); Mon, 8 Jan 2018 12:02:48 -0500 Received: from mga09.intel.com ([134.134.136.24]:48850 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935401AbeAHRCo (ORCPT ); Mon, 8 Jan 2018 12:02:44 -0500 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,330,1511856000"; d="scan'208";a="8771183" Date: Mon, 8 Jan 2018 22:36:55 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Message-ID: <20180108170655.GJ18649@localhost> References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Mon, Jan 08, 2018 at 10:52:01AM +0000, Appana Durga Kedareswara Rao wrote: > Hi Vinod, > > Thanks for the review.... > > >> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct > >xilinx_dma_device *xdev, > >> chan->direction = DMA_MEM_TO_DEV; > >> chan->id = chan_id; > >> chan->tdest = chan_id; > >> + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > >> > >> chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2415,6 > >> +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > >> chan->direction = DMA_DEV_TO_MEM; > >> chan->id = chan_id; > >> chan->tdest = chan_id - xdev->nr_channels; > >> + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > >> > >> chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2629,6 > >> +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) > >> dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); > >> } > >> > >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > > > >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is value > >of addr_width here typically? Usually controllers can support different widths and > >this is a surprise that you support only one value > > Controller supports address width of 32 and 64. Then this should have both 32 and 64 values here > addr_width typical values are 32-bit or 64-bit . > Here addr_width is device-tree parameter... > my understanding of src_addr_widths/dst_addr_widths is, it is a bit mask of the > address with in bytes that DMA supports, please correct if my understanding is wrong. > > Regards, > Kedar. > > > > >-- > >~Vinod -- ~Vinod