From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,1/4] dmaengine: xilinx_dma: populate dma caps properly From: Vinod Koul Message-Id: <20180109044858.GN18649@localhost> Date: Tue, 9 Jan 2018 10:18:58 +0530 To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-ID: T24gTW9uLCBKYW4gMDgsIDIwMTggYXQgMDU6MjU6MDFQTSArMDAwMCwgQXBwYW5hIER1cmdhIEtl ZGFyZXN3YXJhIFJhbyB3cm90ZToKPiBIaSwKPiAKPiA8U25pcD4KPiA+PiA+PiArCXhkZXYtPmNv bW1vbi5kc3RfYWRkcl93aWR0aHMgPSBCSVQoYWRkcl93aWR0aCAvIDgpOwo+ID4+ID4+ICsJeGRl di0+Y29tbW9uLnNyY19hZGRyX3dpZHRocyA9IEJJVChhZGRyX3dpZHRoIC8gOCk7Cj4gPj4gPgo+ ID4+ID5EbyB5b3Ugbm90IHN1cHBvcnQgdHJmIG9mIDFieXRlLCAyIGJ5dGVzLCBvciA0IGJ5dGVz IHdpZGUgdHJhbnNmZXJzPwo+ID4+ID5XaGF0IGlzIHZhbHVlIG9mIGFkZHJfd2lkdGggaGVyZSB0 eXBpY2FsbHk/IFVzdWFsbHkgY29udHJvbGxlcnMgY2FuCj4gPj4gPnN1cHBvcnQgZGlmZmVyZW50 IHdpZHRocyBhbmQgdGhpcyBpcyBhIHN1cnByaXNlIHRoYXQgeW91IHN1cHBvcnQgb25seQo+ID4+ ID5vbmUgdmFsdWUKPiA+Pgo+ID4+IENvbnRyb2xsZXIgc3VwcG9ydHMgYWRkcmVzcyB3aWR0aCBv ZiAzMiBhbmQgNjQuCj4gPgo+ID5UaGVuIHRoaXMgc2hvdWxkIGhhdmUgYm90aCAzMiBhbmQgNjQg dmFsdWVzIGhlcmUKPiAKPiBBZGRyZXNzIHdpZHRoIGlzIGNvbmZpZ3VyYWJsZSBwYXJhbWV0ZXIg YXQgdGhlIGgvdyBsZXZlbC4KPiBTaW5jZSB0aGlzIElQIGlzIGEgc29mdCBJUCB1c2VyIGNhbiBj cmVhdGUgYSBkZXNpZ24gd2l0aCBlaXRoZXIgCj4gMzItYml0IG9yIDY0LWJpdCBhZGRyZXNzIGNv bmZpZ3VyYXRpb24uIAoKYW5kIG5vdCBib3RoIHJpZ2h0PwoKPiBDdXJyZW50bHkgd2UgYXJlIHJl YWRpbmcgdGhpcyBjb25maWd1cmF0aW9uIHRocm91Z2ggZGV2aWNlLXRyZWUgKHhsbngsIGFkZHIt d2lkdGggcHJvcGVydHkpIAo+IGh0dHBzOi8vZ2l0Lmtlcm5lbC5vcmcvcHViL3NjbS9saW51eC9r ZXJuZWwvZ2l0L3Zrb3VsL3NsYXZlLWRtYS5naXQvdHJlZS9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvZG1hL3hpbGlueC94aWxpbnhfZG1hLnR4dCNuMTkKPiBCYXNlZCBvbiB0aGUg aC93IGNvbmZpZ3VyYXRpb24gc2V0dGluZyB0aGUgZHN0X2FkZHJfd2lkdGhzL3NyY19hZGRyX3dp ZHRocyB2YXJpYWJsZXMgaW4gdGhpcyBwYXRjaC4KPiBQbGVhc2UgbGV0IG1lIGtub3cgaWYgeW91 IGFyZSBzdGlsbCBub3QgY2xlYXIgd2l0aCBteSBleHBsYW5hdGlvbiB3aWxsIGV4cGxhaW4gaW4g ZGV0YWlsLi4uIAo+IAo+IFJlZ2FyZHMsCj4gS2VkYXIuCj4gCj4gPgo+ID4+IGFkZHJfd2lkdGgg dHlwaWNhbCB2YWx1ZXMgYXJlIDMyLWJpdCBvciA2NC1iaXQgLgo+ID4+IEhlcmUgYWRkcl93aWR0 aCBpcyBkZXZpY2UtdHJlZSBwYXJhbWV0ZXIuLi4KPiA+PiBteSB1bmRlcnN0YW5kaW5nIG9mIHNy Y19hZGRyX3dpZHRocy9kc3RfYWRkcl93aWR0aHMgaXMsIGl0IGlzIGEgYml0Cj4gPj4gbWFzayBv ZiB0aGUgYWRkcmVzcyB3aXRoIGluIGJ5dGVzIHRoYXQgRE1BIHN1cHBvcnRzLCBwbGVhc2UgY29y cmVjdCBpZiBteQo+ID51bmRlcnN0YW5kaW5nIGlzIHdyb25nLgo+ID4+Cj4gPj4gUmVnYXJkcywK PiA+PiBLZWRhci4KPiA+Pgo+ID4+ID4KPiA+PiA+LS0KPiA+PiA+flZpbm9kCj4gPgo+ID4tLQo+ ID5+Vmlub2QK From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Tue, 9 Jan 2018 10:18:58 +0530 Subject: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly In-Reply-To: References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> Message-ID: <20180109044858.GN18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > > >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> > > >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >What is value of addr_width here typically? Usually controllers can > >> >support different widths and this is a surprise that you support only > >> >one value > >> > >> Controller supports address width of 32 and 64. > > > >Then this should have both 32 and 64 values here > > Address width is configurable parameter at the h/w level. > Since this IP is a soft IP user can create a design with either > 32-bit or 64-bit address configuration. and not both right? > Currently we are reading this configuration through device-tree (xlnx, addr-width property) > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/slave-dma.git/tree/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt#n19 > Based on the h/w configuration setting the dst_addr_widths/src_addr_widths variables in this patch. > Please let me know if you are still not clear with my explanation will explain in detail... > > Regards, > Kedar. > > > > >> addr_width typical values are 32-bit or 64-bit . > >> Here addr_width is device-tree parameter... > >> my understanding of src_addr_widths/dst_addr_widths is, it is a bit > >> mask of the address with in bytes that DMA supports, please correct if my > >understanding is wrong. > >> > >> Regards, > >> Kedar. > >> > >> > > >> >-- > >> >~Vinod > > > >-- > >~Vinod -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932333AbeAIEot (ORCPT + 1 other); Mon, 8 Jan 2018 23:44:49 -0500 Received: from mga14.intel.com ([192.55.52.115]:25891 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752311AbeAIEor (ORCPT ); Mon, 8 Jan 2018 23:44:47 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,334,1511856000"; d="scan'208";a="193307054" Date: Tue, 9 Jan 2018 10:18:58 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Message-ID: <20180109044858.GN18649@localhost> References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > > >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> > > >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >What is value of addr_width here typically? Usually controllers can > >> >support different widths and this is a surprise that you support only > >> >one value > >> > >> Controller supports address width of 32 and 64. > > > >Then this should have both 32 and 64 values here > > Address width is configurable parameter at the h/w level. > Since this IP is a soft IP user can create a design with either > 32-bit or 64-bit address configuration. and not both right? > Currently we are reading this configuration through device-tree (xlnx, addr-width property) > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/slave-dma.git/tree/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt#n19 > Based on the h/w configuration setting the dst_addr_widths/src_addr_widths variables in this patch. > Please let me know if you are still not clear with my explanation will explain in detail... > > Regards, > Kedar. > > > > >> addr_width typical values are 32-bit or 64-bit . > >> Here addr_width is device-tree parameter... > >> my understanding of src_addr_widths/dst_addr_widths is, it is a bit > >> mask of the address with in bytes that DMA supports, please correct if my > >understanding is wrong. > >> > >> Regards, > >> Kedar. > >> > >> > > >> >-- > >> >~Vinod > > > >-- > >~Vinod -- ~Vinod