From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,1/4] dmaengine: xilinx_dma: populate dma caps properly From: Vinod Koul Message-Id: <20180109050449.GO18649@localhost> Date: Tue, 9 Jan 2018 10:34:50 +0530 To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-ID: T24gVHVlLCBKYW4gMDksIDIwMTggYXQgMDQ6NDg6MTBBTSArMDAwMCwgQXBwYW5hIER1cmdhIEtl ZGFyZXN3YXJhIFJhbyB3cm90ZToKPiBIaSwKPiAKPiA+T24gTW9uLCBKYW4gMDgsIDIwMTggYXQg MDU6MjU6MDFQTSArMDAwMCwgQXBwYW5hIER1cmdhIEtlZGFyZXN3YXJhIFJhbwo+ID53cm90ZToK PiA+PiBIaSwKPiA+Pgo+ID4+IDxTbmlwPgo+ID4+ID4+ID4+ICsJeGRldi0+Y29tbW9uLmRzdF9h ZGRyX3dpZHRocyA9IEJJVChhZGRyX3dpZHRoIC8gOCk7Cj4gPj4gPj4gPj4gKwl4ZGV2LT5jb21t b24uc3JjX2FkZHJfd2lkdGhzID0gQklUKGFkZHJfd2lkdGggLyA4KTsKPiA+PiA+PiA+Cj4gPj4g Pj4gPkRvIHlvdSBub3Qgc3VwcG9ydCB0cmYgb2YgMWJ5dGUsIDIgYnl0ZXMsIG9yIDQgYnl0ZXMg d2lkZSB0cmFuc2ZlcnM/Cj4gPj4gPj4gPldoYXQgaXMgdmFsdWUgb2YgYWRkcl93aWR0aCBoZXJl IHR5cGljYWxseT8gVXN1YWxseSBjb250cm9sbGVycwo+ID4+ID4+ID5jYW4gc3VwcG9ydCBkaWZm ZXJlbnQgd2lkdGhzIGFuZCB0aGlzIGlzIGEgc3VycHJpc2UgdGhhdCB5b3UKPiA+PiA+PiA+c3Vw cG9ydCBvbmx5IG9uZSB2YWx1ZQo+ID4+ID4+Cj4gPj4gPj4gQ29udHJvbGxlciBzdXBwb3J0cyBh ZGRyZXNzIHdpZHRoIG9mIDMyIGFuZCA2NC4KPiA+PiA+Cj4gPj4gPlRoZW4gdGhpcyBzaG91bGQg aGF2ZSBib3RoIDMyIGFuZCA2NCB2YWx1ZXMgaGVyZQo+ID4+Cj4gPj4gQWRkcmVzcyB3aWR0aCBp cyBjb25maWd1cmFibGUgcGFyYW1ldGVyIGF0IHRoZSBoL3cgbGV2ZWwuCj4gPj4gU2luY2UgdGhp cyBJUCBpcyBhIHNvZnQgSVAgdXNlciBjYW4gY3JlYXRlIGEgZGVzaWduIHdpdGggZWl0aGVyIDMy LWJpdAo+ID4+IG9yIDY0LWJpdCBhZGRyZXNzIGNvbmZpZ3VyYXRpb24uCj4gPgo+ID5hbmQgbm90 IGJvdGggcmlnaHQ/Cj4gCj4gWWVzIG5vdCBib3RoIGF0IHRoZSBzYW1lIHRpbWUuLi4gCj4gQXhp IGRtYSBjb250cm9sbGVyIGNhbiBiZSBjb25maWd1cmVkIGZvciBlaXRoZXIgMzItYml0IG9yIDY0 LWJpdCBhZGRyZXNzLi4uCgpTbyBteSBzdXNwaWNpb24gd2FzIGNvcnJlY3QuICBJIHdvdWxkIHN1 Z2dlc3QgeW91IHRvIHJlYWQgdXAgb24gdGhlCmRvY3VtZW50YXRpb24gYWdhaW4uIFRoZSBzcmMv ZHN0X2FkZHJfd2lkdGhzIGhhcyBfbm90aGluZ18gdG8gZG8gd2l0aCAzMi82NApiaXQgYWRkcmVz c2VzIHVzZWQuCgpJdCBpcyB0aGUgY2FwYWJpbGl0eSBvZiB0aGUgZG1hIGNvbnRyb2xsZXIgdG8g ZG8gdHJhbnNmZXJzIHdpdGggZGF0YSB3aWR0aCBhcwo4Yml0cywgMTYgYml0cywgc28gb24uIGlL ZXkgaXMgImRhdGEgd2lkdGgiIGFuZCBub3QgYWRkcmVzcyB0eXBlLgpUaGlzIHR5cGljYWxseSB0 cmFuc2xhdGVzIHRvIERNQSBGSUZPIGNvbmZpZ3VyYXRpb24gb2YgdGhlIGNvbnRyb2xsZXIhCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Tue, 9 Jan 2018 10:34:50 +0530 Subject: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly In-Reply-To: References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> <20180109044858.GN18649@localhost> Message-ID: <20180109050449.GO18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao > >wrote: > >> Hi, > >> > >> > >> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> >> > > >> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >> >What is value of addr_width here typically? Usually controllers > >> >> >can support different widths and this is a surprise that you > >> >> >support only one value > >> >> > >> >> Controller supports address width of 32 and 64. > >> > > >> >Then this should have both 32 and 64 values here > >> > >> Address width is configurable parameter at the h/w level. > >> Since this IP is a soft IP user can create a design with either 32-bit > >> or 64-bit address configuration. > > > >and not both right? > > Yes not both at the same time... > Axi dma controller can be configured for either 32-bit or 64-bit address... So my suspicion was correct. I would suggest you to read up on the documentation again. The src/dst_addr_widths has _nothing_ to do with 32/64 bit addresses used. It is the capability of the dma controller to do transfers with data width as 8bits, 16 bits, so on. iKey is "data width" and not address type. This typically translates to DMA FIFO configuration of the controller! -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752224AbeAIFAl (ORCPT + 1 other); Tue, 9 Jan 2018 00:00:41 -0500 Received: from mga11.intel.com ([192.55.52.93]:51919 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750774AbeAIFAj (ORCPT ); Tue, 9 Jan 2018 00:00:39 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,334,1511856000"; d="scan'208";a="8919028" Date: Tue, 9 Jan 2018 10:34:50 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Message-ID: <20180109050449.GO18649@localhost> References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> <20180109044858.GN18649@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao > >wrote: > >> Hi, > >> > >> > >> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> >> > > >> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >> >What is value of addr_width here typically? Usually controllers > >> >> >can support different widths and this is a surprise that you > >> >> >support only one value > >> >> > >> >> Controller supports address width of 32 and 64. > >> > > >> >Then this should have both 32 and 64 values here > >> > >> Address width is configurable parameter at the h/w level. > >> Since this IP is a soft IP user can create a design with either 32-bit > >> or 64-bit address configuration. > > > >and not both right? > > Yes not both at the same time... > Axi dma controller can be configured for either 32-bit or 64-bit address... So my suspicion was correct. I would suggest you to read up on the documentation again. The src/dst_addr_widths has _nothing_ to do with 32/64 bit addresses used. It is the capability of the dma controller to do transfers with data width as 8bits, 16 bits, so on. iKey is "data width" and not address type. This typically translates to DMA FIFO configuration of the controller! -- ~Vinod