From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,1/4] dmaengine: xilinx_dma: populate dma caps properly From: Vinod Koul Message-Id: <20180111062111.GH18649@localhost> Date: Thu, 11 Jan 2018 11:51:11 +0530 To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-ID: T24gVHVlLCBKYW4gMDksIDIwMTggYXQgMDc6MzY6MTFBTSArMDAwMCwgQXBwYW5hIER1cmdhIEtl ZGFyZXN3YXJhIFJhbyB3cm90ZToKPiBIaSwKPiAKPiAJVGhhbmtzIGZvciB0aGUgcmV2aWV3Li4u IAo+IAo+ID5PbiBUdWUsIEphbiAwOSwgMjAxOCBhdCAwNDo0ODoxMEFNICswMDAwLCBBcHBhbmEg RHVyZ2EgS2VkYXJlc3dhcmEgUmFvCj4gPndyb3RlOgo+ID4+IEhpLAo+ID4+Cj4gPj4gPk9uIE1v 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<20180108170655.GJ18649@localhost> <20180109044858.GN18649@localhost> <20180109050449.GO18649@localhost> Message-ID: <20180111062111.GH18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Jan 09, 2018 at 07:36:11AM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > Thanks for the review... > > >On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao > >wrote: > >> Hi, > >> > >> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara > >> >Rao > >> >wrote: > >> >> Hi, > >> >> > >> >> > >> >> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> >> >> > > >> >> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >> >> >What is value of addr_width here typically? Usually controllers > >> >> >> >can support different widths and this is a surprise that you > >> >> >> >support only one value > >> >> >> > >> >> >> Controller supports address width of 32 and 64. > >> >> > > >> >> >Then this should have both 32 and 64 values here > >> >> > >> >> Address width is configurable parameter at the h/w level. > >> >> Since this IP is a soft IP user can create a design with either > >> >> 32-bit or 64-bit address configuration. > >> > > >> >and not both right? > >> > >> Yes not both at the same time... > >> Axi dma controller can be configured for either 32-bit or 64-bit address... > > > >So my suspicion was correct. I would suggest you to read up on the > >documentation again. The src/dst_addr_widths has _nothing_ to do with 32/64 > >bit addresses used. > > > >It is the capability of the dma controller to do transfers with data width as 8bits, > >16 bits, so on. iKey is "data width" and not address type. > >This typically translates to DMA FIFO configuration of the controller! > > Thanks for the detailed explanation... Welcome but I don't understand why you xilinx folks cant wrap your replies, it is *very* hard to read on screens with 80chars > I have gone through the spec again controller does supports 1 byte, 2 > byte, 4 byte up to 128 byte transfers. I think you are talking about length and NOT width > In order to do variable length transfers user needs to drive a valid value > to the tkeep strobe signal at the h/w level. bingo > And user needs to configure the below parameters c_m_axis_mm2s_tdata_width > or c_m_axis_s2mm_tdata_width With desired configuration at the h/w level. > Controller supports data width of 8, 16, 32, 64, 128, 256, 512 and 1,024 > bits (i.e. c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width parameters > range) holy cow, did you read that right. and 1024 bit width, how wide is your FIFO I think you are off the rails here, please get your length and width concepts right, they are NOT same and refer to different things and cannot be used interchangably > > At the s/w level currently we are getting c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width > Configuration as xlnx,datawidth property in the device-tree. > > So proper values for the src/dst_addr width fields should be, datawidth property in bytes. > Please correct me if I am wrong... > > Changes looks like below... > Here width is in bytes based on the h/w configuration... > > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -2411,6 +2411,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > chan->direction = DMA_MEM_TO_DEV; > chan->id = chan_id; > chan->tdest = chan_id; > + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > + xdev->common.src_addr_widths = BIT(width); > > chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > @@ -2428,6 +2430,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > chan->direction = DMA_DEV_TO_MEM; > chan->id = chan_id; > chan->tdest = chan_id - xdev->nr_channels; > + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > + xdev->common.dst_addr_widths = BIT(width); > > chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > > > Regards, > Kedar. > > > > >-- > >~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753776AbeAKGRC (ORCPT + 1 other); Thu, 11 Jan 2018 01:17:02 -0500 Received: from mga01.intel.com ([192.55.52.88]:10540 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750892AbeAKGRA (ORCPT ); Thu, 11 Jan 2018 01:17:00 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,343,1511856000"; d="scan'208";a="18340181" Date: Thu, 11 Jan 2018 11:51:11 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Message-ID: <20180111062111.GH18649@localhost> References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> <20180108170655.GJ18649@localhost> <20180109044858.GN18649@localhost> <20180109050449.GO18649@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Tue, Jan 09, 2018 at 07:36:11AM +0000, Appana Durga Kedareswara Rao wrote: > Hi, > > Thanks for the review... > > >On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao > >wrote: > >> Hi, > >> > >> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara > >> >Rao > >> >wrote: > >> >> Hi, > >> >> > >> >> > >> >> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> >> >> >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > >> >> >> > > >> >> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? > >> >> >> >What is value of addr_width here typically? Usually controllers > >> >> >> >can support different widths and this is a surprise that you > >> >> >> >support only one value > >> >> >> > >> >> >> Controller supports address width of 32 and 64. > >> >> > > >> >> >Then this should have both 32 and 64 values here > >> >> > >> >> Address width is configurable parameter at the h/w level. > >> >> Since this IP is a soft IP user can create a design with either > >> >> 32-bit or 64-bit address configuration. > >> > > >> >and not both right? > >> > >> Yes not both at the same time... > >> Axi dma controller can be configured for either 32-bit or 64-bit address... > > > >So my suspicion was correct. I would suggest you to read up on the > >documentation again. The src/dst_addr_widths has _nothing_ to do with 32/64 > >bit addresses used. > > > >It is the capability of the dma controller to do transfers with data width as 8bits, > >16 bits, so on. iKey is "data width" and not address type. > >This typically translates to DMA FIFO configuration of the controller! > > Thanks for the detailed explanation... Welcome but I don't understand why you xilinx folks cant wrap your replies, it is *very* hard to read on screens with 80chars > I have gone through the spec again controller does supports 1 byte, 2 > byte, 4 byte up to 128 byte transfers. I think you are talking about length and NOT width > In order to do variable length transfers user needs to drive a valid value > to the tkeep strobe signal at the h/w level. bingo > And user needs to configure the below parameters c_m_axis_mm2s_tdata_width > or c_m_axis_s2mm_tdata_width With desired configuration at the h/w level. > Controller supports data width of 8, 16, 32, 64, 128, 256, 512 and 1,024 > bits (i.e. c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width parameters > range) holy cow, did you read that right. and 1024 bit width, how wide is your FIFO I think you are off the rails here, please get your length and width concepts right, they are NOT same and refer to different things and cannot be used interchangably > > At the s/w level currently we are getting c_m_axis_mm2s_tdata_width/ c_m_axis_s2mm_tdata_width > Configuration as xlnx,datawidth property in the device-tree. > > So proper values for the src/dst_addr width fields should be, datawidth property in bytes. > Please correct me if I am wrong... > > Changes looks like below... > Here width is in bytes based on the h/w configuration... > > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -2411,6 +2411,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > chan->direction = DMA_MEM_TO_DEV; > chan->id = chan_id; > chan->tdest = chan_id; > + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > + xdev->common.src_addr_widths = BIT(width); > > chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > @@ -2428,6 +2430,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > chan->direction = DMA_DEV_TO_MEM; > chan->id = chan_id; > chan->tdest = chan_id - xdev->nr_channels; > + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > + xdev->common.dst_addr_widths = BIT(width); > > chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > > > Regards, > Kedar. > > > > >-- > >~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- ~Vinod