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From: Eduardo Habkost <ehabkost@redhat.com>
To: "Gonglei (Arei)" <arei.gonglei@huawei.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit
Date: Mon, 15 Jan 2018 10:23:02 -0200	[thread overview]
Message-ID: <20180115122302.GK6646@localhost.localdomain> (raw)
In-Reply-To: <33183CC9F5247A488A2544077AF19020DA5109CD@DGGEMA505-MBX.china.huawei.com>

On Sat, Jan 13, 2018 at 03:04:44AM +0000, Gonglei (Arei) wrote:
> 
> > -----Original Message-----
> > From: Qemu-devel
> > [mailto:qemu-devel-bounces+arei.gonglei=huawei.com@nongnu.org] On
> > Behalf Of Eduardo Habkost
> > Sent: Tuesday, January 09, 2018 11:45 PM
> > To: qemu-devel@nongnu.org
> > Cc: Paolo Bonzini
> > Subject: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit
> > 
> > Add the feature name and a CPUID_7_0_EDX_SPEC_CTRL macro.
> > 
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> >  target/i386/cpu.h | 1 +
> >  target/i386/cpu.c | 2 +-
> >  2 files changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 07f47997d6..de387c1311 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -667,6 +667,7 @@ typedef uint32_t
> > FeatureWordArray[FEATURE_WORDS];
> > 
> >  #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural
> > Network Instructions */
> >  #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply
> > Accumulation Single Precision */
> > +#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control
> > */
> > 
> >  #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
> >  #define CPUID_XSAVE_XSAVEC     (1U << 1)
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 9f4f949899..1be1642eb2 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -459,7 +459,7 @@ static FeatureWordInfo
> > feature_word_info[FEATURE_WORDS] = {
> >              NULL, NULL, NULL, NULL,
> >              NULL, NULL, NULL, NULL,
> >              NULL, NULL, NULL, NULL,
> > -            NULL, NULL, NULL, NULL,
> > +            NULL, NULL, "spec-ctrl", NULL,
> >              NULL, NULL, NULL, NULL,
> >          },
> >          .cpuid_eax = 7,
> > --
> > 2.14.3
> > 
> Don't we need to pass-through cupid_7_edx to guest when configuring '-cpu host'?
> Otherwise how guests use IBPB/IBRS/STIPB capabilities?

We already do.  See the check for cpu->max_features at
x86_cpu_expand_features().

Do you see something else missing?

-- 
Eduardo

  reply	other threads:[~2018-01-15 12:23 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-09 15:45 [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2) Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 1/7] i386: Change X86CPUDefinition::model_id to const char* Eduardo Habkost
2018-01-09 17:47   ` [Qemu-devel] [PATCH] fixup! " Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 2/7] i386: Add support for SPEC_CTRL MSR Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit Eduardo Habkost
2018-01-13  3:04   ` Gonglei (Arei)
2018-01-15 12:23     ` Eduardo Habkost [this message]
2018-01-16 14:50       ` Gonglei (Arei)
2018-01-09 15:45 ` [Qemu-devel] [PATCH 4/7] i386: Add FEAT_8000_0008_EBX CPUID feature word Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 5/7] i386: Add new -IBRS versions of Intel CPU models Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 6/7] [RFC] i386: Add EPYC-IBPB CPU model Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS Eduardo Habkost
2018-01-09 16:01 ` [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2) no-reply
2018-01-12 19:50 ` Eduardo Habkost
2018-01-15 12:27 ` Eduardo Habkost

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