From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jan 2018 11:13:38 +0100 (CET) Received: from mail.free-electrons.com ([62.4.15.54]:60487 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23994584AbeAPKNEf66zs (ORCPT ); Tue, 16 Jan 2018 11:13:04 +0100 Received: by mail.free-electrons.com (Postfix, from userid 110) id 5903F208C9; Tue, 16 Jan 2018 11:12:58 +0100 (CET) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.free-electrons.com (Postfix) with ESMTPSA id 2AAAA208BE; Tue, 16 Jan 2018 11:12:48 +0100 (CET) From: Alexandre Belloni To: James Hogan , Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs Date: Tue, 16 Jan 2018 11:12:33 +0100 Message-Id: <20180116101240.5393-2-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180116101240.5393-1-alexandre.belloni@free-electrons.com> References: <20180116101240.5393-1-alexandre.belloni@free-electrons.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 62163 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexandre.belloni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..f531d195efc5 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,44 @@ +* Microsemi MIPS CPUs + +Boards with a SoC of the Microsemi MIPS family shall have the following +properties: + +Required properties: +- compatible: "mscc,ocelot" +- mips-hpt-frequency: CPU counter frequency. + + +* Other peripherals: + +o CPU chip regs: + +The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous +functionalities: chip ID, general purpose register for software use, reset +controller, hardware status and configuration, efuses. + +Required properties: +- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@71070000 { + compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + }; + + +o CPU system control: + +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU +endianess, CPU bus control, CPU status. + +Required properties: +- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + }; -- 2.15.1