From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King Date: Sat, 20 Jan 2018 12:29:22 +0000 Subject: [U-Boot] U-Boot, cache speculation side channel attacks and ARM In-Reply-To: <20180120113119.6c957ccc@why.wild-wind.fr.eu.org> References: <20180119215614.GZ4660@bill-the-cat> <20180120104203.7d7b4280@why.wild-wind.fr.eu.org> <20180120113119.6c957ccc@why.wild-wind.fr.eu.org> Message-ID: <20180120122922.GA22862@flint.armlinux.org.uk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sat, Jan 20, 2018 at 11:31:19AM +0000, Marc Zyngier wrote: > Define enough. These patches allow these CPUs to cope with variant-2, > and only variant-2. Variant-1 is still work in progress across all > architectures, variant-3 (aka Meltdown) doesn't concern 32bit ARM > implementations, and only A15 is susceptible to variant-3a. I think you need to be really careful about statements like this. As you know, it is possible to run a 32bit environment in a VM on the 64bit CPUs. So, its entirely possible to run a 32bit setup on a Cortex A72 for example, and that means such a setup _is_ vulnerable to variant 3a. Do people do this? That isn't something we can really know, but I think as long as its allowed, you can bet that someone will, and someone will end up using it in a production environment. So, it can't be ignored. -- Russell King