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From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Ingo Molnar <mingo@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Kim Phillips <kim.phillips@arm.com>,
	Mike Leach <mike.leach@arm.com>,
	Namhyung Kim <namhyung@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Suzuki Poulouse <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: [PATCH 36/43] perf tools: Add mechanic to synthesise CoreSight trace packets
Date: Tue, 23 Jan 2018 10:12:44 -0300	[thread overview]
Message-ID: <20180123131251.28197-37-acme@kernel.org> (raw)
In-Reply-To: <20180123131251.28197-1-acme@kernel.org>

From: Mathieu Poirier <mathieu.poirier@linaro.org>

Once decoded from trace packets information on trace range needs
to be communicated to the perf synthesis infrastructure so that it
is available to the perf tools built-in rendering tools and scripts.

Co-authored-by: Tor Jeremiassen <tor@ti.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Kim Phillips <kim.phillips@arm.com>
Cc: Mike Leach <mike.leach@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1516211539-5166-10-git-send-email-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/cs-etm.c | 168 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 168 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 407095af1456..b9f0a53dfa65 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -453,6 +453,157 @@ static void  cs_etm__set_pid_tid_cpu(struct cs_etm_auxtrace *etm,
 	}
 }
 
+/*
+ * The cs etm packet encodes an instruction range between a branch target
+ * and the next taken branch. Generate sample accordingly.
+ */
+static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq,
+				       struct cs_etm_packet *packet)
+{
+	int ret = 0;
+	struct cs_etm_auxtrace *etm = etmq->etm;
+	struct perf_sample sample = {.ip = 0,};
+	union perf_event *event = etmq->event_buf;
+	u64 start_addr = packet->start_addr;
+	u64 end_addr = packet->end_addr;
+
+	event->sample.header.type = PERF_RECORD_SAMPLE;
+	event->sample.header.misc = PERF_RECORD_MISC_USER;
+	event->sample.header.size = sizeof(struct perf_event_header);
+
+	sample.ip = start_addr;
+	sample.pid = etmq->pid;
+	sample.tid = etmq->tid;
+	sample.addr = end_addr;
+	sample.id = etmq->etm->branches_id;
+	sample.stream_id = etmq->etm->branches_id;
+	sample.period = 1;
+	sample.cpu = packet->cpu;
+	sample.flags = 0;
+	sample.cpumode = PERF_RECORD_MISC_USER;
+
+	ret = perf_session__deliver_synth_event(etm->session, event, &sample);
+
+	if (ret)
+		pr_err(
+		"CS ETM Trace: failed to deliver instruction event, error %d\n",
+		ret);
+
+	return ret;
+}
+
+struct cs_etm_synth {
+	struct perf_tool dummy_tool;
+	struct perf_session *session;
+};
+
+static int cs_etm__event_synth(struct perf_tool *tool,
+			       union perf_event *event,
+			       struct perf_sample *sample __maybe_unused,
+			       struct machine *machine __maybe_unused)
+{
+	struct cs_etm_synth *cs_etm_synth =
+		      container_of(tool, struct cs_etm_synth, dummy_tool);
+
+	return perf_session__deliver_synth_event(cs_etm_synth->session,
+						 event, NULL);
+}
+
+static int cs_etm__synth_event(struct perf_session *session,
+			       struct perf_event_attr *attr, u64 id)
+{
+	struct cs_etm_synth cs_etm_synth;
+
+	memset(&cs_etm_synth, 0, sizeof(struct cs_etm_synth));
+	cs_etm_synth.session = session;
+
+	return perf_event__synthesize_attr(&cs_etm_synth.dummy_tool, attr, 1,
+					   &id, cs_etm__event_synth);
+}
+
+static int cs_etm__synth_events(struct cs_etm_auxtrace *etm,
+				struct perf_session *session)
+{
+	struct perf_evlist *evlist = session->evlist;
+	struct perf_evsel *evsel;
+	struct perf_event_attr attr;
+	bool found = false;
+	u64 id;
+	int err;
+
+	evlist__for_each_entry(evlist, evsel) {
+		if (evsel->attr.type == etm->pmu_type) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found) {
+		pr_debug("No selected events with CoreSight Trace data\n");
+		return 0;
+	}
+
+	memset(&attr, 0, sizeof(struct perf_event_attr));
+	attr.size = sizeof(struct perf_event_attr);
+	attr.type = PERF_TYPE_HARDWARE;
+	attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
+	attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
+			    PERF_SAMPLE_PERIOD;
+	if (etm->timeless_decoding)
+		attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
+	else
+		attr.sample_type |= PERF_SAMPLE_TIME;
+
+	attr.exclude_user = evsel->attr.exclude_user;
+	attr.exclude_kernel = evsel->attr.exclude_kernel;
+	attr.exclude_hv = evsel->attr.exclude_hv;
+	attr.exclude_host = evsel->attr.exclude_host;
+	attr.exclude_guest = evsel->attr.exclude_guest;
+	attr.sample_id_all = evsel->attr.sample_id_all;
+	attr.read_format = evsel->attr.read_format;
+
+	/* create new id val to be a fixed offset from evsel id */
+	id = evsel->id[0] + 1000000000;
+
+	if (!id)
+		id = 1;
+
+	if (etm->synth_opts.branches) {
+		attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
+		attr.sample_period = 1;
+		attr.sample_type |= PERF_SAMPLE_ADDR;
+		err = cs_etm__synth_event(session, &attr, id);
+		if (err)
+			return err;
+		etm->sample_branches = true;
+		etm->branches_sample_type = attr.sample_type;
+		etm->branches_id = id;
+	}
+
+	return 0;
+}
+
+static int cs_etm__sample(struct cs_etm_queue *etmq)
+{
+	int ret;
+	struct cs_etm_packet packet;
+
+	while (1) {
+		ret = cs_etm_decoder__get_packet(etmq->decoder, &packet);
+		if (ret <= 0)
+			return ret;
+
+		/*
+		 * If the packet contains an instruction range, generate an
+		 * instruction sequence event.
+		 */
+		if (packet.sample_type & CS_ETM_RANGE)
+			cs_etm__synth_branch_sample(etmq, &packet);
+	}
+
+	return 0;
+}
+
 static int cs_etm__run_decoder(struct cs_etm_queue *etmq)
 {
 	struct cs_etm_auxtrace *etm = etmq->etm;
@@ -494,6 +645,12 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq)
 
 		etmq->offset += processed;
 		buffer_used += processed;
+
+		/*
+		 * Nothing to do with an error condition, let's hope the next
+		 * chunk will be better.
+		 */
+		err = cs_etm__sample(etmq);
 	} while (buffer.len > buffer_used);
 
 goto more;
@@ -828,6 +985,17 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
 		return 0;
 	}
 
+	if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
+		etm->synth_opts = *session->itrace_synth_opts;
+	} else {
+		itrace_synth_opts__set_default(&etm->synth_opts);
+		etm->synth_opts.callchain = false;
+	}
+
+	err = cs_etm__synth_events(etm, session);
+	if (err)
+		goto err_free_queues;
+
 	err = auxtrace_queues__process_index(&etm->queues, session);
 	if (err)
 		goto err_free_queues;
-- 
2.14.3

WARNING: multiple messages have this Message-ID (diff)
From: acme@kernel.org (Arnaldo Carvalho de Melo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 36/43] perf tools: Add mechanic to synthesise CoreSight trace packets
Date: Tue, 23 Jan 2018 10:12:44 -0300	[thread overview]
Message-ID: <20180123131251.28197-37-acme@kernel.org> (raw)
In-Reply-To: <20180123131251.28197-1-acme@kernel.org>

From: Mathieu Poirier <mathieu.poirier@linaro.org>

Once decoded from trace packets information on trace range needs
to be communicated to the perf synthesis infrastructure so that it
is available to the perf tools built-in rendering tools and scripts.

Co-authored-by: Tor Jeremiassen <tor@ti.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Kim Phillips <kim.phillips@arm.com>
Cc: Mike Leach <mike.leach@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1516211539-5166-10-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/cs-etm.c | 168 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 168 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 407095af1456..b9f0a53dfa65 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -453,6 +453,157 @@ static void  cs_etm__set_pid_tid_cpu(struct cs_etm_auxtrace *etm,
 	}
 }
 
+/*
+ * The cs etm packet encodes an instruction range between a branch target
+ * and the next taken branch. Generate sample accordingly.
+ */
+static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq,
+				       struct cs_etm_packet *packet)
+{
+	int ret = 0;
+	struct cs_etm_auxtrace *etm = etmq->etm;
+	struct perf_sample sample = {.ip = 0,};
+	union perf_event *event = etmq->event_buf;
+	u64 start_addr = packet->start_addr;
+	u64 end_addr = packet->end_addr;
+
+	event->sample.header.type = PERF_RECORD_SAMPLE;
+	event->sample.header.misc = PERF_RECORD_MISC_USER;
+	event->sample.header.size = sizeof(struct perf_event_header);
+
+	sample.ip = start_addr;
+	sample.pid = etmq->pid;
+	sample.tid = etmq->tid;
+	sample.addr = end_addr;
+	sample.id = etmq->etm->branches_id;
+	sample.stream_id = etmq->etm->branches_id;
+	sample.period = 1;
+	sample.cpu = packet->cpu;
+	sample.flags = 0;
+	sample.cpumode = PERF_RECORD_MISC_USER;
+
+	ret = perf_session__deliver_synth_event(etm->session, event, &sample);
+
+	if (ret)
+		pr_err(
+		"CS ETM Trace: failed to deliver instruction event, error %d\n",
+		ret);
+
+	return ret;
+}
+
+struct cs_etm_synth {
+	struct perf_tool dummy_tool;
+	struct perf_session *session;
+};
+
+static int cs_etm__event_synth(struct perf_tool *tool,
+			       union perf_event *event,
+			       struct perf_sample *sample __maybe_unused,
+			       struct machine *machine __maybe_unused)
+{
+	struct cs_etm_synth *cs_etm_synth =
+		      container_of(tool, struct cs_etm_synth, dummy_tool);
+
+	return perf_session__deliver_synth_event(cs_etm_synth->session,
+						 event, NULL);
+}
+
+static int cs_etm__synth_event(struct perf_session *session,
+			       struct perf_event_attr *attr, u64 id)
+{
+	struct cs_etm_synth cs_etm_synth;
+
+	memset(&cs_etm_synth, 0, sizeof(struct cs_etm_synth));
+	cs_etm_synth.session = session;
+
+	return perf_event__synthesize_attr(&cs_etm_synth.dummy_tool, attr, 1,
+					   &id, cs_etm__event_synth);
+}
+
+static int cs_etm__synth_events(struct cs_etm_auxtrace *etm,
+				struct perf_session *session)
+{
+	struct perf_evlist *evlist = session->evlist;
+	struct perf_evsel *evsel;
+	struct perf_event_attr attr;
+	bool found = false;
+	u64 id;
+	int err;
+
+	evlist__for_each_entry(evlist, evsel) {
+		if (evsel->attr.type == etm->pmu_type) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found) {
+		pr_debug("No selected events with CoreSight Trace data\n");
+		return 0;
+	}
+
+	memset(&attr, 0, sizeof(struct perf_event_attr));
+	attr.size = sizeof(struct perf_event_attr);
+	attr.type = PERF_TYPE_HARDWARE;
+	attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
+	attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
+			    PERF_SAMPLE_PERIOD;
+	if (etm->timeless_decoding)
+		attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
+	else
+		attr.sample_type |= PERF_SAMPLE_TIME;
+
+	attr.exclude_user = evsel->attr.exclude_user;
+	attr.exclude_kernel = evsel->attr.exclude_kernel;
+	attr.exclude_hv = evsel->attr.exclude_hv;
+	attr.exclude_host = evsel->attr.exclude_host;
+	attr.exclude_guest = evsel->attr.exclude_guest;
+	attr.sample_id_all = evsel->attr.sample_id_all;
+	attr.read_format = evsel->attr.read_format;
+
+	/* create new id val to be a fixed offset from evsel id */
+	id = evsel->id[0] + 1000000000;
+
+	if (!id)
+		id = 1;
+
+	if (etm->synth_opts.branches) {
+		attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
+		attr.sample_period = 1;
+		attr.sample_type |= PERF_SAMPLE_ADDR;
+		err = cs_etm__synth_event(session, &attr, id);
+		if (err)
+			return err;
+		etm->sample_branches = true;
+		etm->branches_sample_type = attr.sample_type;
+		etm->branches_id = id;
+	}
+
+	return 0;
+}
+
+static int cs_etm__sample(struct cs_etm_queue *etmq)
+{
+	int ret;
+	struct cs_etm_packet packet;
+
+	while (1) {
+		ret = cs_etm_decoder__get_packet(etmq->decoder, &packet);
+		if (ret <= 0)
+			return ret;
+
+		/*
+		 * If the packet contains an instruction range, generate an
+		 * instruction sequence event.
+		 */
+		if (packet.sample_type & CS_ETM_RANGE)
+			cs_etm__synth_branch_sample(etmq, &packet);
+	}
+
+	return 0;
+}
+
 static int cs_etm__run_decoder(struct cs_etm_queue *etmq)
 {
 	struct cs_etm_auxtrace *etm = etmq->etm;
@@ -494,6 +645,12 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq)
 
 		etmq->offset += processed;
 		buffer_used += processed;
+
+		/*
+		 * Nothing to do with an error condition, let's hope the next
+		 * chunk will be better.
+		 */
+		err = cs_etm__sample(etmq);
 	} while (buffer.len > buffer_used);
 
 goto more;
@@ -828,6 +985,17 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
 		return 0;
 	}
 
+	if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
+		etm->synth_opts = *session->itrace_synth_opts;
+	} else {
+		itrace_synth_opts__set_default(&etm->synth_opts);
+		etm->synth_opts.callchain = false;
+	}
+
+	err = cs_etm__synth_events(etm, session);
+	if (err)
+		goto err_free_queues;
+
 	err = auxtrace_queues__process_index(&etm->queues, session);
 	if (err)
 		goto err_free_queues;
-- 
2.14.3

  parent reply	other threads:[~2018-01-23 13:12 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23 13:12 [GIT PULL 00/43] perf/core improvements and changes Arnaldo Carvalho de Melo
2018-01-23 13:12 ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 01/43] perf intel-pt/bts: Do not swap when synthesizing samples Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 02/43] perf evsel: Ensure reserved member of PERF_SAMPLE_CPU is zero in perf_event__synthesize_sample() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 03/43] perf tools: Get rid of unused 'swapped' parameter from perf_event__synthesize_sample() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 04/43] perf tools: Use ui__error() for reporting --fields errors Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 05/43] perf bpf: Don't warn about unavailability of builtin clang, just fallback Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 06/43] perf tools: Move conditional O_CLOEXEC to util.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 07/43] perf symbols: Using O_CLOEXEC in do_open Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 08/43] perf report: Fix regression when decoding intel_pt traces Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 09/43] perf build: Display EXTRA features for VF=1 build Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 10/43] tools include arch: Grab a copy of errno.h for arch's supported by perf Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 11/43] tools include asm-generic: Grab errno.h and errno-base.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 12/43] perf util: Introduce architecture specific errno/name mapping Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 13/43] perf trace: Obtain errno strings by using arch_syscalls__strerrno() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 14/43] perf trace: Remove audit-libs dependency if syscall tables are present Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 15/43] perf vendor events intel: Update Broadwell events to V22 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 16/43] perf vendor events intel: Update BroadwellX events to V13 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 17/43] perf vendor events intel: Update Goldmont events to V12 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 18/43] perf vendor events intel: Update Haswell events to V27 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 19/43] perf vendor events intel: Update HaswellX events to V19 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 20/43] perf vendor events intel: Update IvyBridge events to V20 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 21/43] perf vendor events intel: Update IvyTown " Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 22/43] perf vendor events intel: Update Silvermont events to V14 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 23/43] perf vendor events intel: Update Skylake events to V36 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 24/43] perf vendor events intel: Update SkylakeX events to V1.06 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 25/43] perf vendor events intel: Update BroadwellDE events to V7 Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 26/43] perf vendor events intel: Update IvyBridge files to V20 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 27/43] perf vendor events intel: Update IvyTown " Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 28/43] perf tools: Integrating the CoreSight decoding library Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 29/43] perf tools: Add initial entry point for decoder CoreSight traces Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 30/43] perf tools: Add processing of coresight metadata Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 31/43] perf tools: Add decoder mechanic to support dumping trace data Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 32/43] perf tools: Add support for decoding CoreSight " Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 33/43] perf tools: Add functionality to communicate with the openCSD decoder Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 34/43] pert tools: Add queue management functionality Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 35/43] perf tools: Add full support for CoreSight trace decoding Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` Arnaldo Carvalho de Melo [this message]
2018-01-23 13:12   ` [PATCH 36/43] perf tools: Add mechanic to synthesise CoreSight trace packets Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 37/43] MAINTAINERS: Adding entry for CoreSight trace decoding Arnaldo Carvalho de Melo
2018-01-23 13:12   ` Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 38/43] perf bpf: Remove misplaced __maybe_unused attribute Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 39/43] perf trace: Add --print-sample Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 40/43] perf trace: Do not print from time delta for interrupted syscall lines Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 41/43] perf trace beauty futex: Beautify FUTEX_BITSET_MATCH_ANY Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 42/43] perf evlist: Remove fcntl.h from evlist.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 43/43] perf trace beauty flock: Move to separate object file Arnaldo Carvalho de Melo
2018-01-24 11:15 ` [GIT PULL 00/43] perf/core improvements and changes Ingo Molnar
2018-01-24 11:15   ` Ingo Molnar
2018-01-24 11:15   ` Ingo Molnar

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