Re: [PATCH v2] drm/i915: Implement display w/a #1143

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Jan 22, 2018 at 09:48:46AM -0800, Rodrigo Vivi wrote:
> On Mon, Jan 22, 2018 at 05:41:31PM +0000, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Apparently SKL/KBL/CFL need some manual help to get the
> > programmed HDMI vswing to stick. Implement the relevant
> > workaround (display w/a #1143).
> > 
> > Note that the relevant chicken bits live in a transcoder register
> > even though the bits affect a specific DDI port rather than a
> > specific transcoder. Hence we must pick the correct transcoder
> > register instance based on the port rather than based on the
> > cpu_transcoder.
> > 
> > Also note that for completeness I included support for DDI A/E
> > in the code even though we never have HDMI on those ports.
> > 
> > v2: CFL needs the w/a as well (Rodrigo and Art)
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Art Runyan <arthur.j.runyan@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Pushed to dinq. Thanks for the review.

> 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  8 ++++++--
> >  drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 48 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 10e1269ad6af..2e6d0dc01dc7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7012,8 +7012,12 @@ enum {
> >  #define CHICKEN_TRANS_A         0x420c0
> >  #define CHICKEN_TRANS_B         0x420c4
> >  #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> > -#define PSR2_VSC_ENABLE_PROG_HEADER    (1<<12)
> > -#define PSR2_ADD_VERTICAL_LINE_COUNT   (1<<15)
> > +#define  DDI_TRAINING_OVERRIDE_ENABLE	(1<<19)
> > +#define  DDI_TRAINING_OVERRIDE_VALUE	(1<<18)
> > +#define  DDIE_TRAINING_OVERRIDE_ENABLE	(1<<17) /* CHICKEN_TRANS_A only */
> > +#define  DDIE_TRAINING_OVERRIDE_VALUE	(1<<16) /* CHICKEN_TRANS_A only */
> > +#define  PSR2_ADD_VERTICAL_LINE_COUNT   (1<<15)
> > +#define  PSR2_VSC_ENABLE_PROG_HEADER    (1<<12)
> >  
> >  #define DISP_ARB_CTL	_MMIO(0x45000)
> >  #define  DISP_FBC_MEMORY_WAKE		(1<<31)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6260a882fbe4..e51559be2e3b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> >  					  crtc_state->hdmi_high_tmds_clock_ratio,
> >  					  crtc_state->hdmi_scrambling);
> >  
> > +	/* Display WA #1143: skl,kbl,cfl */
> > +	if (IS_GEN9_BC(dev_priv)) {
> > +		/*
> > +		 * For some reason these chicken bits have been
> > +		 * stuffed into a transcoder register, event though
> > +		 * the bits affect a specific DDI port rather than
> > +		 * a specific transcoder.
> > +		 */
> > +		static const enum transcoder port_to_transcoder[] = {
> > +			[PORT_A] = TRANSCODER_EDP,
> > +			[PORT_B] = TRANSCODER_A,
> > +			[PORT_C] = TRANSCODER_B,
> > +			[PORT_D] = TRANSCODER_C,
> > +			[PORT_E] = TRANSCODER_A,
> > +		};
> > +		enum transcoder transcoder = port_to_transcoder[port];
> > +		u32 val;
> > +
> > +		val = I915_READ(CHICKEN_TRANS(transcoder));
> > +
> > +		if (port == PORT_E)
> > +			val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> > +				DDIE_TRAINING_OVERRIDE_VALUE;
> > +		else
> > +			val |= DDI_TRAINING_OVERRIDE_ENABLE |
> > +				DDI_TRAINING_OVERRIDE_VALUE;
> > +
> > +		I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > +		POSTING_READ(CHICKEN_TRANS(transcoder));
> > +
> > +		udelay(1);
> > +
> > +		if (port == PORT_E)
> > +			val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> > +				 DDIE_TRAINING_OVERRIDE_VALUE);
> > +		else
> > +			val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> > +				 DDI_TRAINING_OVERRIDE_VALUE);
> > +
> > +		I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > +	}
> > +
> >  	/* In HDMI/DVI mode, the port width, and swing/emphasis values
> >  	 * are ignored so nothing special needs to be done besides
> >  	 * enabling the port.
> > -- 
> > 2.13.6
> > 

-- 
Ville Syrjälä
Intel OTC
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