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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 80si132415ywh.548.2018.02.08.12.46.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Feb 2018 12:46:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:47628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejt5Y-0002ms-I6 for alex.bennee@linaro.org; Thu, 08 Feb 2018 15:46:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejsY4-0004Jc-66 for qemu-arm@nongnu.org; Thu, 08 Feb 2018 15:12:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejsY0-0003Hk-RQ for qemu-arm@nongnu.org; Thu, 08 Feb 2018 15:12:00 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:52678 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ejsY0-0003HX-Lc; Thu, 08 Feb 2018 15:11:56 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4295F80125D6; Thu, 8 Feb 2018 20:11:56 +0000 (UTC) Received: from redhat.com (ovpn-120-144.rdu2.redhat.com [10.10.120.144]) by smtp.corp.redhat.com (Postfix) with SMTP id 7A1662166BAE; Thu, 8 Feb 2018 20:11:54 +0000 (UTC) Date: Thu, 8 Feb 2018 22:11:54 +0200 From: "Michael S. Tsirkin" To: Andrey Smirnov Message-ID: <20180208221121-mutt-send-email-mst@kernel.org> References: <20180207042438.15422-1-andrew.smirnov@gmail.com> <20180207042438.15422-11-andrew.smirnov@gmail.com> <20180208194226-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 08 Feb 2018 20:11:56 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 08 Feb 2018 20:11:56 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'mst@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: Re: [Qemu-arm] [PATCH v5 10/14] pci: Add support for Designware IP block X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jason Wang , Marcel Apfelbaum , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , QEMU Developers , "open list:ARM" , Andrey Yurovsky Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: 22NmoQuY69mZ On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote: > >> +#define PCIE_PORT_LINK_CONTROL 0x710 > >> + > >> +#define PCIE_PHY_DEBUG_R1 0x72C > >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4) > >> + > >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C > >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) > >> + > >> +#define PCIE_MSI_ADDR_LO 0x820 > >> +#define PCIE_MSI_ADDR_HI 0x824 > >> +#define PCIE_MSI_INTR0_ENABLE 0x828 > >> +#define PCIE_MSI_INTR0_MASK 0x82C > >> +#define PCIE_MSI_INTR0_STATUS 0x830 > >> + > >> +#define PCIE_ATU_VIEWPORT 0x900 > >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) > >> +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) > >> +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) > >> +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) > >> +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) > >> +#define PCIE_ATU_CR1 0x904 > >> +#define PCIE_ATU_TYPE_MEM (0x0 << 0) > >> +#define PCIE_ATU_TYPE_IO (0x2 << 0) > >> +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) > >> +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) > >> +#define PCIE_ATU_CR2 0x908 > >> +#define PCIE_ATU_ENABLE (0x1 << 31) > >> +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) > >> +#define PCIE_ATU_LOWER_BASE 0x90C > >> +#define PCIE_ATU_UPPER_BASE 0x910 > >> +#define PCIE_ATU_LIMIT 0x914 > >> +#define PCIE_ATU_LOWER_TARGET 0x918 > >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff) > >> +#define PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) > >> +#define PCIE_ATU_UPPER_TARGET 0x91C Can you avoid a PCIE prefix for this btw? Thaks! From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejsY6-0004O9-B6 for qemu-devel@nongnu.org; Thu, 08 Feb 2018 15:12:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejsY5-0003Iy-Cj for qemu-devel@nongnu.org; Thu, 08 Feb 2018 15:12:02 -0500 Date: Thu, 8 Feb 2018 22:11:54 +0200 From: "Michael S. Tsirkin" Message-ID: <20180208221121-mutt-send-email-mst@kernel.org> References: <20180207042438.15422-1-andrew.smirnov@gmail.com> <20180207042438.15422-11-andrew.smirnov@gmail.com> <20180208194226-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrey Smirnov Cc: "open list:ARM" , Peter Maydell , Jason Wang , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Marcel Apfelbaum , QEMU Developers , Andrey Yurovsky On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote: > >> +#define PCIE_PORT_LINK_CONTROL 0x710 > >> + > >> +#define PCIE_PHY_DEBUG_R1 0x72C > >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4) > >> + > >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C > >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) > >> + > >> +#define PCIE_MSI_ADDR_LO 0x820 > >> +#define PCIE_MSI_ADDR_HI 0x824 > >> +#define PCIE_MSI_INTR0_ENABLE 0x828 > >> +#define PCIE_MSI_INTR0_MASK 0x82C > >> +#define PCIE_MSI_INTR0_STATUS 0x830 > >> + > >> +#define PCIE_ATU_VIEWPORT 0x900 > >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) > >> +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) > >> +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) > >> +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) > >> +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) > >> +#define PCIE_ATU_CR1 0x904 > >> +#define PCIE_ATU_TYPE_MEM (0x0 << 0) > >> +#define PCIE_ATU_TYPE_IO (0x2 << 0) > >> +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) > >> +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) > >> +#define PCIE_ATU_CR2 0x908 > >> +#define PCIE_ATU_ENABLE (0x1 << 31) > >> +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) > >> +#define PCIE_ATU_LOWER_BASE 0x90C > >> +#define PCIE_ATU_UPPER_BASE 0x910 > >> +#define PCIE_ATU_LIMIT 0x914 > >> +#define PCIE_ATU_LOWER_TARGET 0x918 > >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff) > >> +#define PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) > >> +#define PCIE_ATU_UPPER_TARGET 0x91C Can you avoid a PCIE prefix for this btw? Thaks!