From: Niklas Cassel <niklas.cassel@axis.com>
To: Vignesh R <vigneshr@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-omap@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] Revert "PCI: dwc: Clear MSI interrupt status after it is handled, not before"
Date: Fri, 9 Feb 2018 14:46:29 +0100 [thread overview]
Message-ID: <20180209134629.GA25931@axis.com> (raw)
In-Reply-To: <20180209120415.17590-2-vigneshr@ti.com>
On Fri, Feb 09, 2018 at 05:34:13PM +0530, Vignesh R wrote:
> Since commit 06e15e6883bed ("PCI: dwc: Clear MSI interrupt status after
> it is handled, not before"), MSI IRQ status in PCIE_MSI_INTR0_STATUS
> register is cleared after calling EP's IRQ handler.
Small nit, the SHA1 is actually:
8c934095fa2f ("PCI: dwc: Clear MSI interrupt status after it is handled, not before")
Acked-by: Niklas Cassel <niklas.cassel@axis.com>
next prev parent reply other threads:[~2018-02-09 13:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-09 12:04 [PATCH 0/3] dra7xx: PCIe IRQ handling rework Vignesh R
2018-02-09 12:04 ` Vignesh R
2018-02-09 12:04 ` [PATCH 1/3] Revert "PCI: dwc: Clear MSI interrupt status after it is handled, not before" Vignesh R
2018-02-09 12:04 ` Vignesh R
2018-02-09 13:46 ` Niklas Cassel [this message]
2018-02-09 12:04 ` [PATCH 2/3] PCI: dwc: pci-dra7xx: Improve MSI IRQ handling Vignesh R
2018-02-09 12:04 ` Vignesh R
2018-02-12 17:58 ` Lorenzo Pieralisi
2018-02-15 4:29 ` Vignesh R
2018-03-01 15:31 ` Vignesh R
2018-03-01 18:18 ` Lorenzo Pieralisi
2018-03-06 15:12 ` Lorenzo Pieralisi
2018-03-09 4:23 ` Vignesh R
2018-03-15 18:10 ` Lorenzo Pieralisi
2018-02-09 12:04 ` [PATCH 3/3] PCI: dwc: pci-dra7xx: Handle legacy and MSI IRQs together Vignesh R
2018-02-09 12:04 ` Vignesh R
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