From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: mmDPREFCLK_CNTL, max_clks_by_state missing for dce60
Date: Sat, 10 Feb 2018 21:25:58 +0000 [thread overview]
Message-ID: <20180210212558.GA1470@freedom> (raw)
Hi,
In my attempt to add the code for dce6 in dc (I base myself on dce80 code), it
seems I miss the mmDPREFCLK_CNTL (dc/dce/dce_clocks.h) register description for
dce60. I have mmDENTIST_DISPCLK_CNTL though.
I miss too the "max_clks_by_state" per power state limits (dc/dce/dce_clocks.c)
for dce60 as I could not find any in amdgpu direct display code. A wild guess
would be those limits are the same than those for dce80.
More I get into DC code, more I get puzzled about what benefits would bring DC
code for the current dce60 hardware: Is dce60 _really_ able to do DP adaptive
sync (freesync)?
regards,
--
Sylvain
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