From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: dmaengine: mv_xor_v2: Fix clock resource by adding a register clock From: Gregory CLEMENT Message-Id: <20180214162733.4591-1-gregory.clement@bootlin.com> Date: Wed, 14 Feb 2018 17:27:33 +0100 To: Vinod Koul , dmaengine@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Antoine Tenart , =?UTF-8?q?Miqu=C3=A8l=20Raynal?= , Nadav Haklai , Shadi Ammouri , Omri Itach , Hanna Hawa , Igal Liberman , Marcin Wojtas List-ID: T24gdGhlIENQMTEwIGNvbXBvbmVudHMgd2hpYyBhcmUgcHJlc2VudCBvbiB0aGUgQXJtYWRhIDdL LzhLIFNvQyB3ZSBuZWVkCnRvIGV4cGxpY2l0bHkgZW5hYmxlIHRoZSByZWdpc3RlcnMgY2xvY2su IEhvd2V2ZXIgaXQgaXMgbm90IG5lZWRlZCBmb3IKdGhlIEFQOHh4IGNvbXBvbmVuZXQsIHRoYXQn cyB3aHkgdGhpcyBjbG9jayBpcyBvcHRpb25hbC4KClNpZ25lZC1vZmYtYnk6IEdyZWdvcnkgQ0xF TUVOVCA8Z3JlZ29yeS5jbGVtZW50QGJvb3RsaW4uY29tPgotLS0KIC4uLi9kZXZpY2V0cmVlL2Jp bmRpbmdzL2RtYS9tdi14b3ItdjIudHh0ICAgICAgICAgIHwgIDYgKysrKystCiBkcml2ZXJzL2Rt YS9tdl94b3JfdjIuYyAgICAgICAgICAgICAgICAgICAgICAgICAgICB8IDIzICsrKysrKysrKysr KysrKysrLS0tLS0KIDIgZmlsZXMgY2hhbmdlZCwgMjMgaW5zZXJ0aW9ucygrKSwgNiBkZWxldGlv bnMoLSkKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1h L212LXhvci12Mi50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1hL212 LXhvci12Mi50eHQKaW5kZXggMjE3YTkwZWFhYmU3Li45YzM4YmJlN2U2ZDcgMTAwNjQ0Ci0tLSBh L0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kbWEvbXYteG9yLXYyLnR4dAorKysg Yi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1hL212LXhvci12Mi50eHQKQEAg LTExLDcgKzExLDExIEBAIFJlcXVpcmVkIHByb3BlcnRpZXM6CiAgIGludGVycnVwdHMuCiAKIE9w dGlvbmFsIHByb3BlcnRpZXM6Ci0tIGNsb2NrczogT3B0aW9uYWwgcmVmZXJlbmNlIHRvIHRoZSBj bG9jayB1c2VkIGJ5IHRoZSBYT1IgZW5naW5lLgorLSBjbG9ja3M6IE9wdGlvbmFsIHJlZmVyZW5j ZSB0byB0aGUgY2xvY2tzIHVzZWQgYnkgdGhlIFhPUiBlbmdpbmUuCistIGNsb2NrLW5hbWVzOiBt YW5kYXRvcnkgaWYgdGhlcmUgaXMgYSBzZWNvbmQgY2xvY2ssIGluIHRoaXMgY2FzZSB0aGUKKyAg IG5hbWUgbXVzdCBiZSAiY29yZSIgZm9yIHRoZSBmaXJzdCBjbG9jayBhbmQgInJlZyIgZm9yIHRo ZSBzZWNvbmQKKyAgIG9uZQorCiAKIEV4YW1wbGU6CiAKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1h L212X3hvcl92Mi5jIGIvZHJpdmVycy9kbWEvbXZfeG9yX3YyLmMKaW5kZXggZjY1MmEwZTBmNWEy Li45M2IzZDgwY2U3MDEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZG1hL212X3hvcl92Mi5jCisrKyBi L2RyaXZlcnMvZG1hL212X3hvcl92Mi5jCkBAIC0xNjMsNiArMTYzLDcgQEAgc3RydWN0IG12X3hv cl92Ml9kZXZpY2UgewogCXZvaWQgX19pb21lbSAqZG1hX2Jhc2U7CiAJdm9pZCBfX2lvbWVtICpn bG9iX2Jhc2U7CiAJc3RydWN0IGNsayAqY2xrOworCXN0cnVjdCBjbGsgKnJlZ19jbGs7CiAJc3Ry dWN0IHRhc2tsZXRfc3RydWN0IGlycV90YXNrbGV0OwogCXN0cnVjdCBsaXN0X2hlYWQgZnJlZV9z d19kZXNjOwogCXN0cnVjdCBkbWFfZGV2aWNlIGRtYWRldjsKQEAgLTc0OSwxMyArNzUwLDI0IEBA IHN0YXRpYyBpbnQgbXZfeG9yX3YyX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYp CiAJaWYgKHJldCkKIAkJcmV0dXJuIHJldDsKIAotCXhvcl9kZXYtPmNsayA9IGRldm1fY2xrX2dl dCgmcGRldi0+ZGV2LCBOVUxMKTsKLQlpZiAoSVNfRVJSKHhvcl9kZXYtPmNsaykgJiYgUFRSX0VS Uih4b3JfZGV2LT5jbGspID09IC1FUFJPQkVfREVGRVIpCisJeG9yX2Rldi0+cmVnX2NsayA9IGRl dm1fY2xrX2dldCgmcGRldi0+ZGV2LCAicmVnIik7CisJaWYgKCFJU19FUlIoeG9yX2Rldi0+cmVn X2NsaykpIHsKKwkJcmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKHhvcl9kZXYtPnJlZ19jbGspOwor CQlpZiAocmV0KQorCQkJcmV0dXJuIHJldDsKKwl9IGVsc2UgaWYgKFBUUl9FUlIoeG9yX2Rldi0+ cmVnX2NsaykgPT0gLUVQUk9CRV9ERUZFUikgewogCQlyZXR1cm4gLUVQUk9CRV9ERUZFUjsKKwl9 CisKKwl4b3JfZGV2LT5jbGsgPSBkZXZtX2Nsa19nZXQoJnBkZXYtPmRldiwgTlVMTCk7CisJaWYg KElTX0VSUih4b3JfZGV2LT5jbGspICYmIFBUUl9FUlIoeG9yX2Rldi0+Y2xrKSA9PSAtRVBST0JF X0RFRkVSKSB7CisJCXJldCA9IEVQUk9CRV9ERUZFUjsKKwkJZ290byBkaXNhYmxlX3JlZ19jbGs7 CisJfQogCWlmICghSVNfRVJSKHhvcl9kZXYtPmNsaykpIHsKIAkJcmV0ID0gY2xrX3ByZXBhcmVf ZW5hYmxlKHhvcl9kZXYtPmNsayk7CiAJCWlmIChyZXQpCi0JCQlyZXR1cm4gcmV0OworCQkJZ290 byBkaXNhYmxlX3JlZ19jbGs7CiAJfQogCiAJcmV0ID0gcGxhdGZvcm1fbXNpX2RvbWFpbl9hbGxv Y19pcnFzKCZwZGV2LT5kZXYsIDEsCkBAIC04NjYsOCArODc4LDkgQEAgc3RhdGljIGludCBtdl94 b3JfdjJfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKIGZyZWVfbXNpX2lycXM6 CiAJcGxhdGZvcm1fbXNpX2RvbWFpbl9mcmVlX2lycXMoJnBkZXYtPmRldik7CiBkaXNhYmxlX2Ns azoKLQlpZiAoIUlTX0VSUih4b3JfZGV2LT5jbGspKQotCQljbGtfZGlzYWJsZV91bnByZXBhcmUo eG9yX2Rldi0+Y2xrKTsKKwljbGtfZGlzYWJsZV91bnByZXBhcmUoeG9yX2Rldi0+Y2xrKTsKK2Rp c2FibGVfcmVnX2NsazoKKwljbGtfZGlzYWJsZV91bnByZXBhcmUoeG9yX2Rldi0+cmVnX2Nsayk7 CiAJcmV0dXJuIHJldDsKIH0KIAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: gregory.clement@bootlin.com (Gregory CLEMENT) Date: Wed, 14 Feb 2018 17:27:33 +0100 Subject: [PATCH] dmaengine: mv_xor_v2: Fix clock resource by adding a register clock Message-ID: <20180214162733.4591-1-gregory.clement@bootlin.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On the CP110 components whic are present on the Armada 7K/8K SoC we need to explicitly enable the registers clock. However it is not needed for the AP8xx componenet, that's why this clock is optional. Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/dma/mv-xor-v2.txt | 6 +++++- drivers/dma/mv_xor_v2.c | 23 +++++++++++++++++----- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt index 217a90eaabe7..9c38bbe7e6d7 100644 --- a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt +++ b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt @@ -11,7 +11,11 @@ Required properties: interrupts. Optional properties: -- clocks: Optional reference to the clock used by the XOR engine. +- clocks: Optional reference to the clocks used by the XOR engine. +- clock-names: mandatory if there is a second clock, in this case the + name must be "core" for the first clock and "reg" for the second + one + Example: diff --git a/drivers/dma/mv_xor_v2.c b/drivers/dma/mv_xor_v2.c index f652a0e0f5a2..93b3d80ce701 100644 --- a/drivers/dma/mv_xor_v2.c +++ b/drivers/dma/mv_xor_v2.c @@ -163,6 +163,7 @@ struct mv_xor_v2_device { void __iomem *dma_base; void __iomem *glob_base; struct clk *clk; + struct clk *reg_clk; struct tasklet_struct irq_tasklet; struct list_head free_sw_desc; struct dma_device dmadev; @@ -749,13 +750,24 @@ static int mv_xor_v2_probe(struct platform_device *pdev) if (ret) return ret; - xor_dev->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER) + xor_dev->reg_clk = devm_clk_get(&pdev->dev, "reg"); + if (!IS_ERR(xor_dev->reg_clk)) { + ret = clk_prepare_enable(xor_dev->reg_clk); + if (ret) + return ret; + } else if (PTR_ERR(xor_dev->reg_clk) == -EPROBE_DEFER) { return -EPROBE_DEFER; + } + + xor_dev->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER) { + ret = EPROBE_DEFER; + goto disable_reg_clk; + } if (!IS_ERR(xor_dev->clk)) { ret = clk_prepare_enable(xor_dev->clk); if (ret) - return ret; + goto disable_reg_clk; } ret = platform_msi_domain_alloc_irqs(&pdev->dev, 1, @@ -866,8 +878,9 @@ static int mv_xor_v2_probe(struct platform_device *pdev) free_msi_irqs: platform_msi_domain_free_irqs(&pdev->dev); disable_clk: - if (!IS_ERR(xor_dev->clk)) - clk_disable_unprepare(xor_dev->clk); + clk_disable_unprepare(xor_dev->clk); +disable_reg_clk: + clk_disable_unprepare(xor_dev->reg_clk); return ret; } -- 2.15.1