From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Clark Subject: [RFC 4/4] drm/msm/mdp5: writeback support Date: Fri, 23 Feb 2018 08:17:54 -0500 Message-ID: <20180223131758.18362-5-robdclark@gmail.com> References: <20180223131758.18362-1-robdclark@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180223131758.18362-1-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Archit Taneja , Laurent Pinchart , Neil Armstrong , David Airlie , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Liviu Dudau , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sushmita Susheelendra , Rob Clark , Sean Paul , Daniel Vetter , freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Brian Starkey , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= List-Id: linux-arm-msm@vger.kernel.org SW4gYSB3YXksIGJhc2VkIG9uIHRoZSBvcmlnaW5hbCB3cml0ZWJhY2sgcGF0Y2ggZnJvbSBKaWxh aSBXYW5nLCBidXQgYQpsb3QgaGFzIHNoaWZ0ZWQgYXJvdW5kIHNpbmNlIHRoZW4uCgpTaWduZWQt b2ZmLWJ5OiBSb2IgQ2xhcmsgPHJvYmRjbGFya0BnbWFpbC5jb20+Ci0tLQogZHJpdmVycy9ncHUv ZHJtL21zbS9NYWtlZmlsZSAgICAgICAgICAgICAgfCAgIDEgKwogZHJpdmVycy9ncHUvZHJtL21z bS9kaXNwL21kcDUvbWRwNV9jcnRjLmMgfCAgMjMgKy0KIGRyaXZlcnMvZ3B1L2RybS9tc20vZGlz cC9tZHA1L21kcDVfa21zLmMgIHwgIDM4ICsrKy0KIGRyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9t ZHA1L21kcDVfa21zLmggIHwgICA3ICstCiBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvbWRwNS9t ZHA1X3diLmMgICB8IDM2NyArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKIGRyaXZlcnMv Z3B1L2RybS9tc20vZHNpL2RzaV9ob3N0LmMgICAgICAgIHwgICA0ICstCiA2IGZpbGVzIGNoYW5n ZWQsIDQzMSBpbnNlcnRpb25zKCspLCA5IGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0 IGRyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9tZHA1L21kcDVfd2IuYwoKZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9tc20vTWFrZWZpbGUgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL01ha2VmaWxl CmluZGV4IGNkNDBjMDUwYjJkNy4uYzlmNTBhZGVmMmRiIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dw dS9kcm0vbXNtL01ha2VmaWxlCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vTWFrZWZpbGUKQEAg LTQ1LDYgKzQ1LDcgQEAgbXNtLXkgOj0gXAogCWRpc3AvbWRwNS9tZHA1X21peGVyLm8gXAogCWRp c3AvbWRwNS9tZHA1X3BsYW5lLm8gXAogCWRpc3AvbWRwNS9tZHA1X3NtcC5vIFwKKwlkaXNwL21k cDUvbWRwNV93Yi5vIFwKIAltc21fYXRvbWljLm8gXAogCW1zbV9kZWJ1Z2ZzLm8gXAogCW1zbV9k cnYubyBcCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvbWRwNS9tZHA1X2Ny dGMuYyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9tZHA1L21kcDVfY3J0Yy5jCmluZGV4IDk4 OTNlNDNiYTZjNS4uYjAwY2E4OGI3NDFkIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vbXNt L2Rpc3AvbWRwNS9tZHA1X2NydGMuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvbWRw NS9tZHA1X2NydGMuYwpAQCAtNDg0LDcgKzQ4NCwxMSBAQCBzdGF0aWMgdm9pZCBtZHA1X2NydGNf YXRvbWljX2VuYWJsZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCiAJfQogCiAJLyogUmVzdG9yZSB2 YmxhbmsgaXJxIGhhbmRsaW5nIGFmdGVyIHBvd2VyIGlzIGVuYWJsZWQgKi8KLQlkcm1fY3J0Y192 Ymxhbmtfb24oY3J0Yyk7CisvLyBUT0RPIHdlIGNhbid0IC0+Z2V0X3NjYW5vdXRfcG9zKCkgZm9y IHdiIChzaW5jZSB2aXJ0dWFsIGludGYpLi4KKy8vIHBlcmhhcHMgZHJtIGNvcmUgc2hvdWxkIGJl IGNsZXZlciBlbm91Z2ggbm90IHRvIGRybV9yZXNldF92YmxhbmtfdGltZXN0YW1wKCkKKy8vIGZv ciB2aXJ0dWFsIGVuY29kZXJzIC8gd3JpdGViYWNrPworCWlmIChtZHA1X2NzdGF0ZS0+cGlwZWxp bmUuaW50Zi0+dHlwZSAhPSBJTlRGX1dCKQorCQlkcm1fY3J0Y192Ymxhbmtfb24oY3J0Yyk7CiAK IAltZHA1X2NydGNfbW9kZV9zZXRfbm9mYihjcnRjKTsKIApAQCAtNTE4LDcgKzUyMiwxMSBAQCBp bnQgbWRwNV9jcnRjX3NldHVwX3BpcGVsaW5lKHN0cnVjdCBkcm1fY3J0YyAqY3J0YywKIAkJdTMy IGNhcHM7CiAJCWludCByZXQ7CiAKLQkJY2FwcyA9IE1EUF9MTV9DQVBfRElTUExBWTsKKwkJaWYg KHBpcGVsaW5lLT5pbnRmLT50eXBlID09IElOVEZfV0IpCisJCQljYXBzID0gTURQX0xNX0NBUF9X QjsKKwkJZWxzZQorCQkJY2FwcyA9IE1EUF9MTV9DQVBfRElTUExBWTsKKwogCQlpZiAobmVlZF9y aWdodF9taXhlcikKIAkJCWNhcHMgfD0gTURQX0xNX0NBUF9QQUlSOwogCkBAIC01NDUsNiArNTUz LDcgQEAgaW50IG1kcDVfY3J0Y19zZXR1cF9waXBlbGluZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMs CiAJbWRwNV9jc3RhdGUtPmVycl9pcnFtYXNrID0gaW50ZjJlcnIoaW50Zi0+bnVtKTsKIAltZHA1 X2NzdGF0ZS0+dmJsYW5rX2lycW1hc2sgPSBpbnRmMnZibGFuayhwaXBlbGluZS0+bWl4ZXIsIGlu dGYpOwogCisvLyBYWFggc2hvdWxkIHdlIGJlIHRyZWF0aW5nIFdCIGFzIGNtZF9tb2RlPz8KIAlp ZiAoKGludGYtPnR5cGUgPT0gSU5URl9EU0kpICYmCiAJICAgIChpbnRmLT5tb2RlID09IE1EUDVf SU5URl9EU0lfTU9ERV9DT01NQU5EKSkgewogCQltZHA1X2NzdGF0ZS0+cHBfZG9uZV9pcnFtYXNr ID0gbG0ycHBkb25lKHBpcGVsaW5lLT5taXhlcik7CkBAIC02MzksOCArNjQ4LDEyIEBAIHN0YXRp YyBpbnQgbWRwNV9jcnRjX2F0b21pY19jaGVjayhzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCiAJfQog CiAJLyogYmFpbCBvdXQgZWFybHkgaWYgdGhlcmUgYXJlbid0IGFueSBwbGFuZXMgKi8KLQlpZiAo IWNudCkKLQkJcmV0dXJuIDA7CisJaWYgKCFjbnQpIHsKKwkJaWYgKCFzdGF0ZS0+YWN0aXZlKQor CQkJcmV0dXJuIDA7CisJCWRldl9lcnIoZGV2LT5kZXYsICIlcyBoYXMgbm8gcGxhbmVzIVxuIiwg Y3J0Yy0+bmFtZSk7CisJCXJldHVybiAtRUlOVkFMOworCX0KIAogCWh3X2NmZyA9IG1kcDVfY2Zn X2dldF9od19jb25maWcobWRwNV9rbXMtPmNmZyk7CiAKQEAgLTExNjAsNyArMTE3Myw3IEBAIHZv aWQgbWRwNV9jcnRjX3dhaXRfZm9yX2NvbW1pdF9kb25lKHN0cnVjdCBkcm1fY3J0YyAqY3J0YykK IAogCWlmIChtZHA1X2NzdGF0ZS0+Y21kX21vZGUpCiAJCW1kcDVfY3J0Y193YWl0X2Zvcl9wcF9k b25lKGNydGMpOwotCWVsc2UKKwllbHNlIGlmIChtZHA1X2NzdGF0ZS0+cGlwZWxpbmUuaW50Zi0+ dHlwZSAhPSBJTlRGX1dCKQogCQltZHA1X2NydGNfd2FpdF9mb3JfZmx1c2hfZG9uZShjcnRjKTsK IH0KIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL21kcDUvbWRwNV9rbXMu YyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9tZHA1L21kcDVfa21zLmMKaW5kZXggMWY0NGQ4 ZjE1Y2UxLi4yMzkwMTA5MDU2MzcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlz cC9tZHA1L21kcDVfa21zLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL21kcDUvbWRw NV9rbXMuYwpAQCAtNDI3LDcgKzQyNyw4IEBAIHN0YXRpYyBpbnQgbW9kZXNldF9pbml0KHN0cnVj dCBtZHA1X2ttcyAqbWRwNV9rbXMpCiAJICogdGhlIE1EUDUgaW50ZXJmYWNlcykgdGhhbiB0aGUg bnVtYmVyIG9mIGxheWVyIG1peGVycyBwcmVzZW50IGluIEhXLAogCSAqIGJ1dCBsZXQncyBiZSBz YWZlIGhlcmUgYW55d2F5CiAJICovCi0JbnVtX2NydGNzID0gbWluKHByaXYtPm51bV9lbmNvZGVy cywgbWRwNV9rbXMtPm51bV9od21peGVycyk7CisJbnVtX2NydGNzID0gbWluKHByaXYtPm51bV9l bmNvZGVycyArIGh3X2NmZy0+d2IuY291bnQsCisJCQltZHA1X2ttcy0+bnVtX2h3bWl4ZXJzKTsK IAogCS8qCiAJICogQ29uc3RydWN0IHBsYW5lcyBlcXVhbGluZyB0aGUgbnVtYmVyIG9mIGh3IHBp cGVzLCBhbmQgQ1JUQ3MgZm9yIHRoZQpAQCAtNDgyLDYgKzQ4MywzMyBAQCBzdGF0aWMgaW50IG1v ZGVzZXRfaW5pdChzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVfa21zKQogCQllbmNvZGVyLT5wb3NzaWJs ZV9jcnRjcyA9ICgxIDw8IHByaXYtPm51bV9jcnRjcykgLSAxOwogCX0KIAorCS8qCisJICogTGFz dGx5LCBjb25zdHJ1Y3Qgd3JpdGViYWNrIGNvbm5lY3RvcnMuCisJICovCisJZm9yIChpID0gMDsg aSA8IGh3X2NmZy0+d2IuY291bnQ7IGkrKykgeworCQlzdHJ1Y3QgZHJtX3dyaXRlYmFja19jb25u ZWN0b3IgKndiX2Nvbm47CisJCXN0cnVjdCBtZHA1X2N0bCAqY3RsOworCisJCWN0bCA9IG1kcDVf Y3RsbV9yZXF1ZXN0KG1kcDVfa21zLT5jdGxtLCAtMSk7CisJCWlmICghY3RsKSB7CisJCQlkZXZf ZXJyKGRldi0+ZGV2LAorCQkJCSJmYWlsZWQgdG8gYWxsb2NhdGUgY3RsIGZvciB3cml0ZWJhY2sg JWRcbiIsIGkpOworCQkJY29udGludWU7CisJCX0KKworCQl3Yl9jb25uID0gbWRwNV93Yl9jb25u ZWN0b3JfaW5pdChkZXYsIGN0bCwKKwkJCQlod19jZmctPndiLmluc3RhbmNlc1tpXS5pZCk7CisJ CWlmIChJU19FUlIod2JfY29ubikpIHsKKwkJCXJldCA9IFBUUl9FUlIod2JfY29ubik7CisJCQlk ZXZfZXJyKGRldi0+ZGV2LAorCQkJCSJmYWlsZWQgdG8gY29uc3RydWN0IHdyaXRlYmFjayBjb25u ZWN0b3IgJWQgKCVkKVxuIiwKKwkJCQlpLCByZXQpOworCQkJZ290byBmYWlsOworCQl9CisKKwkJ d2JfY29ubi0+ZW5jb2Rlci5wb3NzaWJsZV9jcnRjcyA9ICgxIDw8IHByaXYtPm51bV9jcnRjcykg LSAxOworCX0KKwogCXJldHVybiAwOwogCiBmYWlsOgpAQCAtNTU1LDYgKzU4MywxMCBAQCBzdGF0 aWMgYm9vbCBtZHA1X2dldF9zY2Fub3V0cG9zKHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIHVuc2ln bmVkIGludCBwaXBlLAogCQlyZXR1cm4gZmFsc2U7CiAJfQogCisJLyogdW5zdXBwb3J0ZWQgZm9y IHdyaXRlYmFjazogKi8KKwlpZiAoZW5jb2Rlci0+ZW5jb2Rlcl90eXBlID09IERSTV9NT0RFX0VO Q09ERVJfVklSVFVBTCkKKwkJcmV0dXJuIGZhbHNlOworCiAJdnN3ID0gbW9kZS0+Y3J0Y192c3lu Y19lbmQgLSBtb2RlLT5jcnRjX3ZzeW5jX3N0YXJ0OwogCXZicCA9IG1vZGUtPmNydGNfdnRvdGFs IC0gbW9kZS0+Y3J0Y192c3luY19lbmQ7CiAKQEAgLTYxMCw2ICs2NDIsMTAgQEAgc3RhdGljIHUz MiBtZHA1X2dldF92YmxhbmtfY291bnRlcihzdHJ1Y3QgZHJtX2RldmljZSAqZGV2LCB1bnNpZ25l ZCBpbnQgcGlwZSkKIAlpZiAoIWVuY29kZXIpCiAJCXJldHVybiAwOwogCisJLyogdW5zdXBwb3J0 ZWQgZm9yIHdyaXRlYmFjazogKi8KKwlpZiAoZW5jb2Rlci0+ZW5jb2Rlcl90eXBlID09IERSTV9N T0RFX0VOQ09ERVJfVklSVFVBTCkKKwkJcmV0dXJuIDA7CisKIAlyZXR1cm4gbWRwNV9lbmNvZGVy X2dldF9mcmFtZWNvdW50KGVuY29kZXIpOwogfQogCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k cm0vbXNtL2Rpc3AvbWRwNS9tZHA1X2ttcy5oIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL21k cDUvbWRwNV9rbXMuaAppbmRleCA0MjVhMDNkMjEzZTUuLmJlMGY5M2VmMzNlMSAxMDA2NDQKLS0t IGEvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL21kcDUvbWRwNV9rbXMuaAorKysgYi9kcml2ZXJz L2dwdS9kcm0vbXNtL2Rpc3AvbWRwNS9tZHA1X2ttcy5oCkBAIC0xOCw2ICsxOCw4IEBACiAjaWZu ZGVmIF9fTURQNV9LTVNfSF9fCiAjZGVmaW5lIF9fTURQNV9LTVNfSF9fCiAKKyNpbmNsdWRlIDxk cm0vZHJtX3dyaXRlYmFjay5oPgorCiAjaW5jbHVkZSAibXNtX2Rydi5oIgogI2luY2x1ZGUgIm1z bV9rbXMuaCIKICNpbmNsdWRlICJkaXNwL21kcF9rbXMuaCIKQEAgLTI1MSw3ICsyNTMsNyBAQCBz dGF0aWMgaW5saW5lIHVpbnQzMl90IGludGYydmJsYW5rKHN0cnVjdCBtZHA1X2h3X21peGVyICpt aXhlciwKIAkJcmV0dXJuIE1EUDVfSVJRX1BJTkdfUE9OR18wX1JEX1BUUiA8PCBtaXhlci0+cHA7 CiAKIAlpZiAoaW50Zi0+dHlwZSA9PSBJTlRGX1dCKQotCQlyZXR1cm4gTURQNV9JUlFfV0JfMl9E T05FOworCQlyZXR1cm4gTURQNV9JUlFfV0JfMl9ET05FIHwgTURQNV9JUlFfV0JfMF9ET05FIHwg TURQNV9JUlFfV0JfMV9ET05FOwogCiAJc3dpdGNoIChpbnRmLT5udW0pIHsKIAljYXNlIDA6ICBy ZXR1cm4gTURQNV9JUlFfSU5URjBfVlNZTkM7CkBAIC0zMzAsNCArMzMyLDcgQEAgc3RhdGljIGlu bGluZSBpbnQgbWRwNV9jbWRfZW5jb2Rlcl9zZXRfc3BsaXRfZGlzcGxheSgKIH0KICNlbmRpZgog CitzdHJ1Y3QgZHJtX3dyaXRlYmFja19jb25uZWN0b3IgKm1kcDVfd2JfY29ubmVjdG9yX2luaXQo c3RydWN0IGRybV9kZXZpY2UgKmRldiwKKwkJc3RydWN0IG1kcDVfY3RsICpjdGwsIHVuc2lnbmVk IHdiX2lkKTsKKwogI2VuZGlmIC8qIF9fTURQNV9LTVNfSF9fICovCmRpZmYgLS1naXQgYS9kcml2 ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvbWRwNS9tZHA1X3diLmMgYi9kcml2ZXJzL2dwdS9kcm0vbXNt L2Rpc3AvbWRwNS9tZHA1X3diLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAw MDAwLi4zZGFiZDBhMWFhOGIKLS0tIC9kZXYvbnVsbAorKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNt L2Rpc3AvbWRwNS9tZHA1X3diLmMKQEAgLTAsMCArMSwzNjcgQEAKKy8qCisgKiBDb3B5cmlnaHQg KEMpIDIwMTggUmVkIEhhdAorICogQXV0aG9yOiBSb2IgQ2xhcmsgPHJvYmRjbGFya0BnbWFpbC5j b20+CisgKgorICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0 cmlidXRlIGl0IGFuZC9vciBtb2RpZnkgaXQKKyAqIHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05V IEdlbmVyYWwgUHVibGljIExpY2Vuc2UgdmVyc2lvbiAyIGFzIHB1Ymxpc2hlZCBieQorICogdGhl IEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4KKyAqCisgKiBUaGlzIHByb2dyYW0gaXMgZGlzdHJp YnV0ZWQgaW4gdGhlIGhvcGUgdGhhdCBpdCB3aWxsIGJlIHVzZWZ1bCwgYnV0IFdJVEhPVVQKKyAq IEFOWSBXQVJSQU5UWTsgd2l0aG91dCBldmVuIHRoZSBpbXBsaWVkIHdhcnJhbnR5IG9mIE1FUkNI QU5UQUJJTElUWSBvcgorICogRklUTkVTUyBGT1IgQSBQQVJUSUNVTEFSIFBVUlBPU0UuICBTZWUg dGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIGZvcgorICogbW9yZSBkZXRhaWxzLgorICoK KyAqIFlvdSBzaG91bGQgaGF2ZSByZWNlaXZlZCBhIGNvcHkgb2YgdGhlIEdOVSBHZW5lcmFsIFB1 YmxpYyBMaWNlbnNlIGFsb25nIHdpdGgKKyAqIHRoaXMgcHJvZ3JhbS4gIElmIG5vdCwgc2VlIDxo dHRwOi8vd3d3LmdudS5vcmcvbGljZW5zZXMvPi4KKyAqLworCisjaW5jbHVkZSAibWRwNV9rbXMu aCIKKworLyoKKyAqIFdyaXRlYmFjayBjb25uZWN0b3IvZW5jb2RlciBpbXBsZW1lbnRhdGlvbjoK KyAqLworCitzdHJ1Y3QgbWRwNV93Yl9jb25uZWN0b3IgeworCXN0cnVjdCBkcm1fd3JpdGViYWNr X2Nvbm5lY3RvciBiYXNlOworCisJdTMyIG5mb3JtYXRzOworCXUzMiBmb3JtYXRzWzMyXTsKKwor CXVuc2lnbmVkIGlkOworCXN0cnVjdCBtZHA1X2N0bCAqY3RsOworCXN0cnVjdCBtZHA1X2ludGVy ZmFjZSAqaW50ZjsKKworCXN0cnVjdCBtZHBfaXJxIHdiX2RvbmU7Cit9OworI2RlZmluZSB0b19t ZHA1X3diX2Nvbm5lY3Rvcih4KSBjb250YWluZXJfb2YoeCwgc3RydWN0IG1kcDVfd2JfY29ubmVj dG9yLCBiYXNlKQorCisKK3N0YXRpYyB2b2lkIG1kcDVfd2JfY29ubmVjdG9yX2F0b21pY19jb21t aXQoc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvciwKKwkJc3RydWN0IGRybV93cml0ZWJh Y2tfam9iICpqb2IpOworCitzdGF0aWMgaW50IG1kcDVfd2JfY29ubmVjdG9yX2dldF9tb2Rlcyhz dHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9yKQoreworCXN0cnVjdCBkcm1fZGV2aWNlICpk ZXYgPSBjb25uZWN0b3ItPmRldjsKKworCXJldHVybiBkcm1fYWRkX21vZGVzX25vZWRpZChjb25u ZWN0b3IsIGRldi0+bW9kZV9jb25maWcubWF4X3dpZHRoLAorCQkJZGV2LT5tb2RlX2NvbmZpZy5t YXhfaGVpZ2h0KTsKK30KKworc3RhdGljIGVudW0gZHJtX21vZGVfc3RhdHVzCittZHA1X3diX2Nv bm5lY3Rvcl9tb2RlX3ZhbGlkKHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IsCisJCXN0 cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlKQoreworCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYg PSBjb25uZWN0b3ItPmRldjsKKwlzdHJ1Y3QgZHJtX21vZGVfY29uZmlnICptb2RlX2NvbmZpZyA9 ICZkZXYtPm1vZGVfY29uZmlnOworCWludCB3ID0gbW9kZS0+aGRpc3BsYXksIGggPSBtb2RlLT52 ZGlzcGxheTsKKworCWlmICgodyA8IG1vZGVfY29uZmlnLT5taW5fd2lkdGgpIHx8ICh3ID4gbW9k ZV9jb25maWctPm1heF93aWR0aCkpCisJCXJldHVybiBNT0RFX0JBRF9IVkFMVUU7CisKKwlpZiAo KGggPCBtb2RlX2NvbmZpZy0+bWluX2hlaWdodCkgfHwgKGggPiBtb2RlX2NvbmZpZy0+bWF4X2hl aWdodCkpCisJCXJldHVybiBNT0RFX0JBRF9WVkFMVUU7CisKKwlyZXR1cm4gTU9ERV9PSzsKK30K KworY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3JfaGVscGVyX2Z1bmNzIG1kcDVfd2JfY29ubmVj dG9yX2hlbHBlcl9mdW5jcyA9IHsKKwkuZ2V0X21vZGVzID0gbWRwNV93Yl9jb25uZWN0b3JfZ2V0 X21vZGVzLAorCS5tb2RlX3ZhbGlkID0gbWRwNV93Yl9jb25uZWN0b3JfbW9kZV92YWxpZCwKKwku YXRvbWljX2NvbW1pdCA9IG1kcDVfd2JfY29ubmVjdG9yX2F0b21pY19jb21taXQsCit9OworCitz dGF0aWMgZW51bSBkcm1fY29ubmVjdG9yX3N0YXR1cworbWRwNV93Yl9jb25uZWN0b3JfZGV0ZWN0 KHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IsIGJvb2wgZm9yY2UpCit7CisJcmV0dXJu IGNvbm5lY3Rvcl9zdGF0dXNfZGlzY29ubmVjdGVkOworfQorCitzdGF0aWMgdm9pZCBtZHA1X3di X2Nvbm5lY3Rvcl9kZXN0cm95KHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IpCit7CisJ ZHJtX2Nvbm5lY3Rvcl9jbGVhbnVwKGNvbm5lY3Rvcik7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1 Y3QgZHJtX2Nvbm5lY3Rvcl9mdW5jcyBtZHA1X3diX2Nvbm5lY3Rvcl9mdW5jcyA9IHsKKwkucmVz ZXQgPSBkcm1fYXRvbWljX2hlbHBlcl9jb25uZWN0b3JfcmVzZXQsCisJLmRldGVjdCA9IG1kcDVf d2JfY29ubmVjdG9yX2RldGVjdCwKKwkuZmlsbF9tb2RlcyA9IGRybV9oZWxwZXJfcHJvYmVfc2lu Z2xlX2Nvbm5lY3Rvcl9tb2RlcywKKwkuZGVzdHJveSA9IG1kcDVfd2JfY29ubmVjdG9yX2Rlc3Ry b3ksCisJLmF0b21pY19kdXBsaWNhdGVfc3RhdGUgPSBkcm1fYXRvbWljX2hlbHBlcl9jb25uZWN0 b3JfZHVwbGljYXRlX3N0YXRlLAorCS5hdG9taWNfZGVzdHJveV9zdGF0ZSA9IGRybV9hdG9taWNf aGVscGVyX2Nvbm5lY3Rvcl9kZXN0cm95X3N0YXRlLAorfTsKKworc3RhdGljIGludAorbWRwNV93 Yl9lbmNvZGVyX2F0b21pY19jaGVjayhzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsCisJCXN0 cnVjdCBkcm1fY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwKKwkJc3RydWN0IGRybV9jb25uZWN0b3Jf c3RhdGUgKmNvbm5fc3RhdGUpCit7CisJc3RydWN0IG1zbV9kcm1fcHJpdmF0ZSAqcHJpdiA9IGVu Y29kZXItPmRldi0+ZGV2X3ByaXZhdGU7CisJc3RydWN0IG1kcDVfY3J0Y19zdGF0ZSAqbWRwNV9j c3RhdGUgPSB0b19tZHA1X2NydGNfc3RhdGUoY3J0Y19zdGF0ZSk7CisJc3RydWN0IG1kcDVfd2Jf Y29ubmVjdG9yICptZHA1X3diID0gdG9fbWRwNV93Yl9jb25uZWN0b3IoCisJCXRvX3diX2Nvbm5l Y3Rvcihjb25uX3N0YXRlLT5jb25uZWN0b3IpKTsKKwlzdHJ1Y3QgZHJtX2ZyYW1lYnVmZmVyICpm YjsKKwljb25zdCBzdHJ1Y3QgbXNtX2Zvcm1hdCAqZm9ybWF0OworCWNvbnN0IHN0cnVjdCBtZHBf Zm9ybWF0ICptZHBfZm10OworCXN0cnVjdCBkcm1fZm9ybWF0X25hbWVfYnVmIGZvcm1hdF9uYW1l OworCWludCByZXQ7CisKKwlpZiAoIWNvbm5fc3RhdGUtPndyaXRlYmFja19qb2IgfHwgIWNvbm5f c3RhdGUtPndyaXRlYmFja19qb2ItPmZiKQorCQlyZXR1cm4gMDsKKworCWZiID0gY29ubl9zdGF0 ZS0+d3JpdGViYWNrX2pvYi0+ZmI7CisKKwlEQkcoIndiWyV1XTogY2hlY2sgd3JpdGViYWNrICV1 eCV1QCVzIiwgbWRwNV93Yi0+aWQsCisJCWZiLT53aWR0aCwgZmItPmhlaWdodCwKKwkJZHJtX2dl dF9mb3JtYXRfbmFtZShmYi0+Zm9ybWF0LT5mb3JtYXQsICZmb3JtYXRfbmFtZSkpOworCisJZm9y bWF0ID0gbWRwX2dldF9mb3JtYXQocHJpdi0+a21zLCBmYi0+Zm9ybWF0LT5mb3JtYXQpOworCWlm ICghZm9ybWF0KSB7CisJCURCRygiSW52YWxpZCBwaXhlbCBmb3JtYXQhIik7CisJCXJldHVybiAt RUlOVkFMOworCX0KKworCW1kcF9mbXQgPSB0b19tZHBfZm9ybWF0KGZvcm1hdCk7CisJaWYgKE1E UF9GT1JNQVRfSVNfWVVWKG1kcF9mbXQpKSB7CisJCXN3aXRjaCAobWRwX2ZtdC0+Y2hyb21hX3Nh bXBsZSkgeworCQljYXNlIENIUk9NQV80MjA6CisJCWNhc2UgQ0hST01BX0gyVjE6CisJCQkvKiBz dXBwb3J0ZWQgKi8KKwkJCWJyZWFrOworCQljYXNlIENIUk9NQV9IMVYyOgorCQlkZWZhdWx0Ogor CQkJREJHKCJ1bnN1cHBvcnRlZCB3YiBjaHJvbWEgc2FtcD0lZFxuIiwKKwkJCQltZHBfZm10LT5j aHJvbWFfc2FtcGxlKTsKKwkJCXJldHVybiAtRUlOVkFMOworCQl9CisJfQorCisJLyogVE9ETyBJ IHRoaW5rIHdlIHdvdWxkIHByZWZlciB0byBoYXZlIHByb3BlciBwcmVwYXJlX2ZiKCkvY2xlYW51 cF9mYigpCisJICogdmZ1bmNzLCBhcyB3aXRoIHBsYW5lLi4gIEFsc28sIHdoZXJlIHRvIHVucHJl cGFyZT8KKwkgKi8KKwlyZXQgPSBtc21fZnJhbWVidWZmZXJfcHJlcGFyZShmYiwgcHJpdi0+a21z LT5hc3BhY2UpOworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKKwltZHA1X2NzdGF0ZS0+Y3Rs ID0gbWRwNV93Yi0+Y3RsOworCW1kcDVfY3N0YXRlLT5waXBlbGluZS5pbnRmID0gbWRwNV93Yi0+ aW50ZjsKKwltZHA1X2NzdGF0ZS0+ZGVmZXJfc3RhcnQgPSB0cnVlOworCisJcmV0dXJuIDA7Cit9 CisKK3N0YXRpYyB2b2lkCit3Yl9jc2Nfc2V0dXAoc3RydWN0IG1kcDVfa21zICptZHA1X2ttcywg dTMyIHdiX2lkLCBzdHJ1Y3QgY3NjX2NmZyAqY3NjKQoreworCXVpbnQzMl90ICBpOworCXVpbnQz Ml90ICptYXRyaXg7CisKKwlpZiAodW5saWtlbHkoIWNzYykpCisJCXJldHVybjsKKworCW1hdHJp eCA9IGNzYy0+bWF0cml4OworCW1kcDVfd3JpdGUobWRwNV9rbXMsIFJFR19NRFA1X1dCX0NTQ19N QVRSSVhfQ09FRkZfMCh3Yl9pZCksCisJCU1EUDVfV0JfQ1NDX01BVFJJWF9DT0VGRl8wX0NPRUZG XzExKG1hdHJpeFswXSkgfAorCQlNRFA1X1dCX0NTQ19NQVRSSVhfQ09FRkZfMF9DT0VGRl8xMiht YXRyaXhbMV0pKTsKKwltZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9DU0NfTUFUUklY X0NPRUZGXzEod2JfaWQpLAorCQlNRFA1X1dCX0NTQ19NQVRSSVhfQ09FRkZfMV9DT0VGRl8xMyht YXRyaXhbMl0pIHwKKwkJTURQNV9XQl9DU0NfTUFUUklYX0NPRUZGXzFfQ09FRkZfMjEobWF0cml4 WzNdKSk7CisJbWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfQ1NDX01BVFJJWF9DT0VG Rl8yKHdiX2lkKSwKKwkJTURQNV9XQl9DU0NfTUFUUklYX0NPRUZGXzJfQ09FRkZfMjIobWF0cml4 WzRdKSB8CisJCU1EUDVfV0JfQ1NDX01BVFJJWF9DT0VGRl8yX0NPRUZGXzIzKG1hdHJpeFs1XSkp OworCW1kcDVfd3JpdGUobWRwNV9rbXMsIFJFR19NRFA1X1dCX0NTQ19NQVRSSVhfQ09FRkZfMyh3 Yl9pZCksCisJCU1EUDVfV0JfQ1NDX01BVFJJWF9DT0VGRl8zX0NPRUZGXzMxKG1hdHJpeFs2XSkg fAorCQlNRFA1X1dCX0NTQ19NQVRSSVhfQ09FRkZfM19DT0VGRl8zMihtYXRyaXhbN10pKTsKKwlt ZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9DU0NfTUFUUklYX0NPRUZGXzQod2JfaWQp LAorCQlNRFA1X1dCX0NTQ19NQVRSSVhfQ09FRkZfNF9DT0VGRl8zMyhtYXRyaXhbOF0pKTsKKwor CWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKGNzYy0+cHJlX2JpYXMpOyBpKyspIHsKKwkJdWlu dDMyX3QgKnByZV9jbGFtcCA9IGNzYy0+cHJlX2NsYW1wOworCQl1aW50MzJfdCAqcG9zdF9jbGFt cCA9IGNzYy0+cG9zdF9jbGFtcDsKKworCQltZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9X Ql9DU0NfQ09NUF9QUkVDTEFNUCh3Yl9pZCwgaSksCisJCQlNRFA1X1dCX0NTQ19DT01QX1BSRUNM QU1QX1JFR19ISUdIKHByZV9jbGFtcFsyKmkrMV0pIHwKKwkJCU1EUDVfV0JfQ1NDX0NPTVBfUFJF Q0xBTVBfUkVHX0xPVyhwcmVfY2xhbXBbMippXSkpOworCisJCW1kcDVfd3JpdGUobWRwNV9rbXMs IFJFR19NRFA1X1dCX0NTQ19DT01QX1BPU1RDTEFNUCh3Yl9pZCwgaSksCisJCQlNRFA1X1dCX0NT Q19DT01QX1BPU1RDTEFNUF9SRUdfSElHSChwb3N0X2NsYW1wWzIqaSsxXSkgfAorCQkJTURQNV9X Ql9DU0NfQ09NUF9QT1NUQ0xBTVBfUkVHX0xPVyhwb3N0X2NsYW1wWzIqaV0pKTsKKworCQltZHA1 X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9DU0NfQ09NUF9QUkVCSUFTKHdiX2lkLCBpKSwK KwkJCU1EUDVfV0JfQ1NDX0NPTVBfUFJFQklBU19SRUdfVkFMVUUoY3NjLT5wcmVfYmlhc1tpXSkp OworCisJCW1kcDVfd3JpdGUobWRwNV9rbXMsIFJFR19NRFA1X1dCX0NTQ19DT01QX1BPU1RCSUFT KHdiX2lkLCBpKSwKKwkJCU1EUDVfV0JfQ1NDX0NPTVBfUE9TVEJJQVNfUkVHX1ZBTFVFKGNzYy0+ cG9zdF9iaWFzW2ldKSk7CisJfQorfQorCitzdGF0aWMgdm9pZAorbWRwNV93Yl9jb25uZWN0b3Jf YXRvbWljX2NvbW1pdChzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9yLAorCQlzdHJ1Y3Qg ZHJtX3dyaXRlYmFja19qb2IgKmpvYikKK3sKKwlzdHJ1Y3QgbXNtX2RybV9wcml2YXRlICpwcml2 ID0gY29ubmVjdG9yLT5kZXYtPmRldl9wcml2YXRlOworCXN0cnVjdCBtZHA1X2ttcyAqbWRwNV9r bXMgPSB0b19tZHA1X2ttcyh0b19tZHBfa21zKHByaXYtPmttcykpOworCXN0cnVjdCBkcm1fY29u bmVjdG9yX3N0YXRlICpjb25uX3N0YXRlID0gY29ubmVjdG9yLT5zdGF0ZTsKKwlzdHJ1Y3QgZHJt X3dyaXRlYmFja19jb25uZWN0b3IgKndiX2Nvbm4gPSB0b193Yl9jb25uZWN0b3IoY29ubmVjdG9y KTsKKwlzdHJ1Y3QgbWRwNV9jcnRjX3N0YXRlICptZHA1X2NydGNfc3RhdGUgPQorCQl0b19tZHA1 X2NydGNfc3RhdGUod2JfY29ubi0+ZW5jb2Rlci5jcnRjLT5zdGF0ZSk7CisJc3RydWN0IG1kcDVf d2JfY29ubmVjdG9yICptZHA1X3diID0gdG9fbWRwNV93Yl9jb25uZWN0b3Iod2JfY29ubik7CisJ c3RydWN0IGRybV9mcmFtZWJ1ZmZlciAqZmIgPSBqb2ItPmZiOworCXN0cnVjdCBkcm1fZm9ybWF0 X25hbWVfYnVmIGZvcm1hdF9uYW1lOworCWNvbnN0IHN0cnVjdCBtZHBfZm9ybWF0ICpmbXQgPQor CQl0b19tZHBfZm9ybWF0KG1kcF9nZXRfZm9ybWF0KHByaXYtPmttcywgZmItPmZvcm1hdC0+Zm9y bWF0KSk7CisJdTMyIHlzdHJpZGUwLCB5c3RyaWRlMSwgb3V0c2l6ZTsKKwl1MzIgZHN0X2Zvcm1h dCwgcGF0dGVybiwgb3Btb2RlID0gMDsKKworCURCRygid2JbJXVdOiBraWNrIHdyaXRlYmFjayAl dXgldUAlcyIsIG1kcDVfd2ItPmlkLAorCQlmYi0+d2lkdGgsIGZiLT5oZWlnaHQsCisJCWRybV9n ZXRfZm9ybWF0X25hbWUoZmItPmZvcm1hdC0+Zm9ybWF0LCAmZm9ybWF0X25hbWUpKTsKKworCS8q IHF1ZXVlIGpvYiBiZWZvcmUgYW55dGhpbmcgdGhhdCBjYW4gdHJpZ2dlciBjb21wbGV0aW9uIGly cSAqLworCWRybV93cml0ZWJhY2tfcXVldWVfam9iKHdiX2Nvbm4sIGpvYik7CisJY29ubl9zdGF0 ZS0+d3JpdGViYWNrX2pvYiA9IE5VTEw7CisKKwltZHBfaXJxX3JlZ2lzdGVyKCZtZHA1X2ttcy0+ YmFzZSwgJm1kcDVfd2ItPndiX2RvbmUpOworCisJaWYgKE1EUF9GT1JNQVRfSVNfWVVWKGZtdCkp IHsKKwkJd2JfY3NjX3NldHVwKG1kcDVfa21zLCBtZHA1X3diLT5pZCwKKwkJCW1kcF9nZXRfZGVm YXVsdF9jc2NfY2ZnKENTQ19SR0IyWVVWKSk7CisKKwkJb3Btb2RlIHw9IE1EUDVfV0JfRFNUX09Q X01PREVfQ1NDX0VOIHwKKwkJCU1EUDVfV0JfRFNUX09QX01PREVfQ1NDX1NSQ19EQVRBX0ZPUk1B VChEQVRBX0ZPUk1BVF9SR0IpIHwKKwkJCU1EUDVfV0JfRFNUX09QX01PREVfQ1NDX0RTVF9EQVRB X0ZPUk1BVChEQVRBX0ZPUk1BVF9ZVVYpOworCisJCXN3aXRjaCAoZm10LT5jaHJvbWFfc2FtcGxl KSB7CisJCWNhc2UgQ0hST01BXzQyMDoKKwkJY2FzZSBDSFJPTUFfSDJWMToKKwkJCW9wbW9kZSB8 PSBNRFA1X1dCX0RTVF9PUF9NT0RFX0NIUk9NQV9EV05fU0FNUExFX0VOOworCQkJYnJlYWs7CisJ CWNhc2UgQ0hST01BX0gxVjI6CisJCWRlZmF1bHQ6CisJCQlXQVJOKDEsICJ1bnN1cHBvcnRlZCB3 YiBjaHJvbWEgc2FtcD0lZFxuIiwKKwkJCQlmbXQtPmNocm9tYV9zYW1wbGUpOworCQkJcmV0dXJu OworCQl9CisJfQorCisJZHN0X2Zvcm1hdCA9IE1EUDVfV0JfRFNUX0ZPUk1BVF9EU1RfQ0hST01B X1NBTVAoZm10LT5jaHJvbWFfc2FtcGxlKSB8CisJCU1EUDVfV0JfRFNUX0ZPUk1BVF9XUklURV9Q TEFORVMoZm10LT5mZXRjaF90eXBlKSB8CisJCU1EUDVfV0JfRFNUX0ZPUk1BVF9EU1RDM19PVVQo Zm10LT5icGNfYSkgfAorCQlNRFA1X1dCX0RTVF9GT1JNQVRfRFNUQzJfT1VUKGZtdC0+YnBjX3Ip IHwKKwkJTURQNV9XQl9EU1RfRk9STUFUX0RTVEMxX09VVChmbXQtPmJwY19iKSB8CisJCU1EUDVf V0JfRFNUX0ZPUk1BVF9EU1RDMF9PVVQoZm10LT5icGNfZykgfAorCQlDT05EKGZtdC0+dW5wYWNr X3RpZ2h0LCBNRFA1X1dCX0RTVF9GT1JNQVRfUEFDS19USUdIVCkgfAorCQlNRFA1X1dCX0RTVF9G T1JNQVRfUEFDS19DT1VOVChmbXQtPnVucGFja19jb3VudCAtIDEpIHwKKwkJTURQNV9XQl9EU1Rf Rk9STUFUX0RTVF9CUFAoZm10LT5jcHAgLSAxKTsKKworCWlmIChmbXQtPmJwY19hIHx8IGZtdC0+ YWxwaGFfZW5hYmxlKSB7CisJCWRzdF9mb3JtYXQgfD0gTURQNV9XQl9EU1RfRk9STUFUX0RTVEMz X0VOOworCQlpZiAoIWZtdC0+YWxwaGFfZW5hYmxlKQorCQkJZHN0X2Zvcm1hdCB8PSBNRFA1X1dC X0RTVF9GT1JNQVRfRFNUX0FMUEhBX1g7CisJfQorCisJcGF0dGVybiA9IE1EUDVfV0JfRFNUX1BB Q0tfUEFUVEVSTl9FTEVNRU5UMyhmbXQtPnVucGFja1szXSkgfAorCQlNRFA1X1dCX0RTVF9QQUNL X1BBVFRFUk5fRUxFTUVOVDIoZm10LT51bnBhY2tbMl0pIHwKKwkJTURQNV9XQl9EU1RfUEFDS19Q QVRURVJOX0VMRU1FTlQxKGZtdC0+dW5wYWNrWzFdKSB8CisJCU1EUDVfV0JfRFNUX1BBQ0tfUEFU VEVSTl9FTEVNRU5UMChmbXQtPnVucGFja1swXSk7CisKKwl5c3RyaWRlMCA9IE1EUDVfV0JfRFNU X1lTVFJJREUwX0RTVDBfWVNUUklERShmYi0+cGl0Y2hlc1swXSkgfAorCQlNRFA1X1dCX0RTVF9Z U1RSSURFMF9EU1QxX1lTVFJJREUoZmItPnBpdGNoZXNbMV0pOworCXlzdHJpZGUxID0gTURQNV9X Ql9EU1RfWVNUUklERTFfRFNUMl9ZU1RSSURFKGZiLT5waXRjaGVzWzJdKSB8CisJCU1EUDVfV0Jf RFNUX1lTVFJJREUxX0RTVDNfWVNUUklERShmYi0+cGl0Y2hlc1szXSk7CisKKwkvKiBnZXQgdGhl IG91dHB1dCByZXNvbHV0aW9uIGZyb20gV0IgZGV2aWNlICovCisJb3V0c2l6ZSA9IE1EUDVfV0Jf T1VUX1NJWkVfRFNUX0goZmItPmhlaWdodCkgfAorCQlNRFA1X1dCX09VVF9TSVpFX0RTVF9XKGZi LT53aWR0aCk7CisKKwltZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9BTFBIQV9YX1ZB TFVFKG1kcDVfd2ItPmlkKSwgMHhmZik7CisJbWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVf V0JfRFNUX0ZPUk1BVChtZHA1X3diLT5pZCksIGRzdF9mb3JtYXQpOworCW1kcDVfd3JpdGUobWRw NV9rbXMsIFJFR19NRFA1X1dCX0RTVF9PUF9NT0RFKG1kcDVfd2ItPmlkKSwgb3Btb2RlKTsKKwlt ZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9EU1RfUEFDS19QQVRURVJOKG1kcDVfd2It PmlkKSwgcGF0dGVybik7CisJbWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfRFNUX1lT VFJJREUwKG1kcDVfd2ItPmlkKSwgeXN0cmlkZTApOworCW1kcDVfd3JpdGUobWRwNV9rbXMsIFJF R19NRFA1X1dCX0RTVF9ZU1RSSURFMShtZHA1X3diLT5pZCksIHlzdHJpZGUxKTsKKwltZHA1X3dy aXRlKG1kcDVfa21zLCBSRUdfTURQNV9XQl9PVVRfU0laRShtZHA1X3diLT5pZCksIG91dHNpemUp OworCisJbWRwNV9jcnRjX3NldF9waXBlbGluZSh3Yl9jb25uLT5lbmNvZGVyLmNydGMpOworCisJ bWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfRFNUMF9BRERSKG1kcDVfd2ItPmlkKSwK KwkJbXNtX2ZyYW1lYnVmZmVyX2lvdmEoZmIsIHByaXYtPmttcy0+YXNwYWNlLCAwKSk7CisJbWRw NV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfRFNUMV9BRERSKG1kcDVfd2ItPmlkKSwKKwkJ bXNtX2ZyYW1lYnVmZmVyX2lvdmEoZmIsIHByaXYtPmttcy0+YXNwYWNlLCAxKSk7CisJbWRwNV93 cml0ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfRFNUMl9BRERSKG1kcDVfd2ItPmlkKSwKKwkJbXNt X2ZyYW1lYnVmZmVyX2lvdmEoZmIsIHByaXYtPmttcy0+YXNwYWNlLCAyKSk7CisJbWRwNV93cml0 ZShtZHA1X2ttcywgUkVHX01EUDVfV0JfRFNUM19BRERSKG1kcDVfd2ItPmlkKSwKKwkJbXNtX2Zy YW1lYnVmZmVyX2lvdmEoZmIsIHByaXYtPmttcy0+YXNwYWNlLCAzKSk7CisKKwkvKiBOb3RpZnkg Y3RsIHRoYXQgd2IgYnVmZmVyIGlzIHJlYWR5IHRvIHRyaWdnZXIgc3RhcnQgKi8KKwltZHA1X2N0 bF9jb21taXQobWRwNV93Yi0+Y3RsLCAmbWRwNV9jcnRjX3N0YXRlLT5waXBlbGluZSwKKwkJTURQ NV9DVExfRkxVU0hfV0IsIHRydWUpOworCisJbWRwNV9jdGxfc2V0X2VuY29kZXJfc3RhdGUobWRw NV93Yi0+Y3RsLAorCQkmbWRwNV9jcnRjX3N0YXRlLT5waXBlbGluZSwgdHJ1ZSk7Cit9CisKK3N0 YXRpYyB2b2lkIG1kcDVfd2JfZG9uZV9pcnEoc3RydWN0IG1kcF9pcnEgKmlycSwgdWludDMyX3Qg aXJxc3RhdHVzKQoreworCXN0cnVjdCBtZHA1X3diX2Nvbm5lY3RvciAqbWRwNV93YiA9CisJCWNv bnRhaW5lcl9vZihpcnEsIHN0cnVjdCBtZHA1X3diX2Nvbm5lY3Rvciwgd2JfZG9uZSk7CisJc3Ry dWN0IG1kcDVfY3J0Y19zdGF0ZSAqbWRwNV9jcnRjX3N0YXRlID0KKwkJdG9fbWRwNV9jcnRjX3N0 YXRlKG1kcDVfd2ItPmJhc2UuZW5jb2Rlci5jcnRjLT5zdGF0ZSk7CisJc3RydWN0IG1zbV9kcm1f cHJpdmF0ZSAqcHJpdiA9IG1kcDVfd2ItPmJhc2UuYmFzZS5kZXYtPmRldl9wcml2YXRlOworCisJ bWRwX2lycV91bnJlZ2lzdGVyKHRvX21kcF9rbXMocHJpdi0+a21zKSwgJm1kcDVfd2ItPndiX2Rv bmUpOworCisJbWRwNV9jdGxfc2V0X2VuY29kZXJfc3RhdGUobWRwNV93Yi0+Y3RsLAorCQkmbWRw NV9jcnRjX3N0YXRlLT5waXBlbGluZSwgZmFsc2UpOworCisJZHJtX3dyaXRlYmFja19zaWduYWxf Y29tcGxldGlvbigmbWRwNV93Yi0+YmFzZSwgMCk7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg ZHJtX2VuY29kZXJfaGVscGVyX2Z1bmNzIG1kcDVfd2JfZW5jb2Rlcl9oZWxwZXJfZnVuY3MgPSB7 CisJLmF0b21pY19jaGVjayA9IG1kcDVfd2JfZW5jb2Rlcl9hdG9taWNfY2hlY2ssCit9OworCitz dHJ1Y3QgZHJtX3dyaXRlYmFja19jb25uZWN0b3IgKgorbWRwNV93Yl9jb25uZWN0b3JfaW5pdChz dHJ1Y3QgZHJtX2RldmljZSAqZGV2LCBzdHJ1Y3QgbWRwNV9jdGwgKmN0bCwKKwkJdW5zaWduZWQg d2JfaWQpCit7CisJc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvciA9IE5VTEw7CisJc3Ry dWN0IG1kcDVfd2JfY29ubmVjdG9yICptZHA1X3diOworCisJbWRwNV93YiA9IGt6YWxsb2Moc2l6 ZW9mKCptZHA1X3diKSwgR0ZQX0tFUk5FTCk7CisJaWYgKCFtZHA1X3diKQorCQlyZXR1cm4gRVJS X1BUUigtRU5PTUVNKTsKKworCW1kcDVfd2ItPmlkID0gd2JfaWQ7CisJbWRwNV93Yi0+Y3RsID0g Y3RsOworCisJLyogY29uc3RydWN0IGEgZHVtbXkgaW50ZiBmb3IgV0I6ICovCisvLyBUT0RPIHVu LWlubGluZSB0aGlzIChhbmQgYWxzbyBpbiBpbnRlcmZhY2VfaW5pdCgpKQorCW1kcDVfd2ItPmlu dGYgPSBremFsbG9jKHNpemVvZigqbWRwNV93Yi0+aW50ZiksIEdGUF9LRVJORUwpOworCW1kcDVf d2ItPmludGYtPm51bSA9IC0xOworCW1kcDVfd2ItPmludGYtPnR5cGUgPSBJTlRGX1dCOworCW1k cDVfd2ItPmludGYtPm1vZGUgPSBNRFA1X0lOVEZfV0JfTU9ERV9MSU5FOworCW1kcDVfd2ItPmlu dGYtPmlkeCA9IC0xOworCisJbWRwNV93Yi0+d2JfZG9uZS5pcnEgPSBtZHA1X3diX2RvbmVfaXJx OworLy8gVE9ETyBqdXN0IHJlZ2lzdGVyIGZvciBhbGwgd2IgaXJxJ3MgdW50aWwgSSBmaWd1cmUg b3V0IHRoZSBtYXBwaW5nLi4KKwltZHA1X3diLT53Yl9kb25lLmlycW1hc2sgPSBNRFA1X0lSUV9X Ql8wX0RPTkUgfCBNRFA1X0lSUV9XQl8xX0RPTkUgfCBNRFA1X0lSUV9XQl8yX0RPTkU7CisKKwlj b25uZWN0b3IgPSAmbWRwNV93Yi0+YmFzZS5iYXNlOworCisJZHJtX2Nvbm5lY3Rvcl9oZWxwZXJf YWRkKGNvbm5lY3RvciwgJm1kcDVfd2JfY29ubmVjdG9yX2hlbHBlcl9mdW5jcyk7CisKKwltZHA1 X3diLT5uZm9ybWF0cyA9IG1kcF9nZXRfZm9ybWF0cyhtZHA1X3diLT5mb3JtYXRzLAorCQlBUlJB WV9TSVpFKG1kcDVfd2ItPmZvcm1hdHMpLCBmYWxzZSk7CisKKwlkcm1fd3JpdGViYWNrX2Nvbm5l Y3Rvcl9pbml0KGRldiwKKwkJJm1kcDVfd2ItPmJhc2UsCisJCSZtZHA1X3diX2Nvbm5lY3Rvcl9m dW5jcywKKwkJJm1kcDVfd2JfZW5jb2Rlcl9oZWxwZXJfZnVuY3MsCisJCW1kcDVfd2ItPmZvcm1h dHMsCisJCW1kcDVfd2ItPm5mb3JtYXRzKTsKKworCWNvbm5lY3Rvci0+aW50ZXJsYWNlX2FsbG93 ZWQgPSAwOworCWNvbm5lY3Rvci0+ZG91Ymxlc2Nhbl9hbGxvd2VkID0gMDsKKworCXJldHVybiAm bWRwNV93Yi0+YmFzZTsKK30KZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZHNpL2Rz aV9ob3N0LmMgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2RzaS9kc2lfaG9zdC5jCmluZGV4IDdhMDNh OTQ4OTcwOC4uNDIyZjUyNGY3NTYyIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rz aS9kc2lfaG9zdC5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZHNpL2RzaV9ob3N0LmMKQEAg LTc0MSw3ICs3NDEsNyBAQCBzdGF0aWMgdm9pZCBkc2lfaW50cl9jdHJsKHN0cnVjdCBtc21fZHNp X2hvc3QgKm1zbV9ob3N0LCB1MzIgbWFzaywgaW50IGVuYWJsZSkKIAllbHNlCiAJCWludHIgJj0g fm1hc2s7CiAKLQlEQkcoImludHI9JXggZW5hYmxlPSVkIiwgaW50ciwgZW5hYmxlKTsKKwlWRVJC KCJpbnRyPSV4IGVuYWJsZT0lZCIsIGludHIsIGVuYWJsZSk7CiAKIAlkc2lfd3JpdGUobXNtX2hv c3QsIFJFR19EU0lfSU5UUl9DVFJMLCBpbnRyKTsKIAlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZt c21faG9zdC0+aW50cl9sb2NrLCBmbGFncyk7CkBAIC0xNDY1LDcgKzE0NjUsNyBAQCBzdGF0aWMg aXJxcmV0dXJuX3QgZHNpX2hvc3RfaXJxKGludCBpcnEsIHZvaWQgKnB0cikKIAlkc2lfd3JpdGUo bXNtX2hvc3QsIFJFR19EU0lfSU5UUl9DVFJMLCBpc3IpOwogCXNwaW5fdW5sb2NrX2lycXJlc3Rv cmUoJm1zbV9ob3N0LT5pbnRyX2xvY2ssIGZsYWdzKTsKIAotCURCRygiaXNyPTB4JXgsIGlkPSVk IiwgaXNyLCBtc21faG9zdC0+aWQpOworCVZFUkIoImlzcj0weCV4LCBpZD0lZCIsIGlzciwgbXNt X2hvc3QtPmlkKTsKIAogCWlmIChpc3IgJiBEU0lfSVJRX0VSUk9SKQogCQlkc2lfZXJyb3IobXNt X2hvc3QpOwotLSAKMi4xNC4zCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpGcmVlZHJlbm8gbWFpbGluZyBsaXN0CkZyZWVkcmVub0BsaXN0cy5mcmVlZGVz a3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9m cmVlZHJlbm8K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751868AbeBWNUz (ORCPT ); Fri, 23 Feb 2018 08:20:55 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:44919 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751839AbeBWNUx (ORCPT ); Fri, 23 Feb 2018 08:20:53 -0500 X-Google-Smtp-Source: AG47ELscco9mAzWPXBe+boTTJmm22rwlR8/IgiJcK6nMFgeNdhl1DjlojMJCGUwPmi1IolEd4OV+gg== From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Brian Starkey , Liviu Dudau , Rob Clark , David Airlie , Archit Taneja , Daniel Vetter , Laurent Pinchart , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Neil Armstrong , Sean Paul , Sushmita Susheelendra , linux-kernel@vger.kernel.org Subject: [RFC 4/4] drm/msm/mdp5: writeback support Date: Fri, 23 Feb 2018 08:17:54 -0500 Message-Id: <20180223131758.18362-5-robdclark@gmail.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180223131758.18362-1-robdclark@gmail.com> References: <20180223131758.18362-1-robdclark@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In a way, based on the original writeback patch from Jilai Wang, but a lot has shifted around since then. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 23 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 38 +++- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 7 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_wb.c | 367 ++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 4 +- 6 files changed, 431 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/mdp5/mdp5_wb.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index cd40c050b2d7..c9f50adef2db 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -45,6 +45,7 @@ msm-y := \ disp/mdp5/mdp5_mixer.o \ disp/mdp5/mdp5_plane.o \ disp/mdp5/mdp5_smp.o \ + disp/mdp5/mdp5_wb.o \ msm_atomic.o \ msm_debugfs.o \ msm_drv.o \ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index 9893e43ba6c5..b00ca88b741d 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -484,7 +484,11 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, } /* Restore vblank irq handling after power is enabled */ - drm_crtc_vblank_on(crtc); +// TODO we can't ->get_scanout_pos() for wb (since virtual intf).. +// perhaps drm core should be clever enough not to drm_reset_vblank_timestamp() +// for virtual encoders / writeback? + if (mdp5_cstate->pipeline.intf->type != INTF_WB) + drm_crtc_vblank_on(crtc); mdp5_crtc_mode_set_nofb(crtc); @@ -518,7 +522,11 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, u32 caps; int ret; - caps = MDP_LM_CAP_DISPLAY; + if (pipeline->intf->type == INTF_WB) + caps = MDP_LM_CAP_WB; + else + caps = MDP_LM_CAP_DISPLAY; + if (need_right_mixer) caps |= MDP_LM_CAP_PAIR; @@ -545,6 +553,7 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, mdp5_cstate->err_irqmask = intf2err(intf->num); mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); +// XXX should we be treating WB as cmd_mode?? if ((intf->type == INTF_DSI) && (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); @@ -639,8 +648,12 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, } /* bail out early if there aren't any planes */ - if (!cnt) - return 0; + if (!cnt) { + if (!state->active) + return 0; + dev_err(dev->dev, "%s has no planes!\n", crtc->name); + return -EINVAL; + } hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); @@ -1160,7 +1173,7 @@ void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) if (mdp5_cstate->cmd_mode) mdp5_crtc_wait_for_pp_done(crtc); - else + else if (mdp5_cstate->pipeline.intf->type != INTF_WB) mdp5_crtc_wait_for_flush_done(crtc); } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 1f44d8f15ce1..239010905637 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -427,7 +427,8 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) * the MDP5 interfaces) than the number of layer mixers present in HW, * but let's be safe here anyway */ - num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); + num_crtcs = min(priv->num_encoders + hw_cfg->wb.count, + mdp5_kms->num_hwmixers); /* * Construct planes equaling the number of hw pipes, and CRTCs for the @@ -482,6 +483,33 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; } + /* + * Lastly, construct writeback connectors. + */ + for (i = 0; i < hw_cfg->wb.count; i++) { + struct drm_writeback_connector *wb_conn; + struct mdp5_ctl *ctl; + + ctl = mdp5_ctlm_request(mdp5_kms->ctlm, -1); + if (!ctl) { + dev_err(dev->dev, + "failed to allocate ctl for writeback %d\n", i); + continue; + } + + wb_conn = mdp5_wb_connector_init(dev, ctl, + hw_cfg->wb.instances[i].id); + if (IS_ERR(wb_conn)) { + ret = PTR_ERR(wb_conn); + dev_err(dev->dev, + "failed to construct writeback connector %d (%d)\n", + i, ret); + goto fail; + } + + wb_conn->encoder.possible_crtcs = (1 << priv->num_crtcs) - 1; + } + return 0; fail: @@ -555,6 +583,10 @@ static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe, return false; } + /* unsupported for writeback: */ + if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) + return false; + vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; vbp = mode->crtc_vtotal - mode->crtc_vsync_end; @@ -610,6 +642,10 @@ static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) if (!encoder) return 0; + /* unsupported for writeback: */ + if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) + return 0; + return mdp5_encoder_get_framecount(encoder); } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index 425a03d213e5..be0f93ef33e1 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -18,6 +18,8 @@ #ifndef __MDP5_KMS_H__ #define __MDP5_KMS_H__ +#include + #include "msm_drv.h" #include "msm_kms.h" #include "disp/mdp_kms.h" @@ -251,7 +253,7 @@ static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer, return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp; if (intf->type == INTF_WB) - return MDP5_IRQ_WB_2_DONE; + return MDP5_IRQ_WB_2_DONE | MDP5_IRQ_WB_0_DONE | MDP5_IRQ_WB_1_DONE; switch (intf->num) { case 0: return MDP5_IRQ_INTF0_VSYNC; @@ -330,4 +332,7 @@ static inline int mdp5_cmd_encoder_set_split_display( } #endif +struct drm_writeback_connector *mdp5_wb_connector_init(struct drm_device *dev, + struct mdp5_ctl *ctl, unsigned wb_id); + #endif /* __MDP5_KMS_H__ */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_wb.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_wb.c new file mode 100644 index 000000000000..3dabd0a1aa8b --- /dev/null +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_wb.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2018 Red Hat + * Author: Rob Clark + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "mdp5_kms.h" + +/* + * Writeback connector/encoder implementation: + */ + +struct mdp5_wb_connector { + struct drm_writeback_connector base; + + u32 nformats; + u32 formats[32]; + + unsigned id; + struct mdp5_ctl *ctl; + struct mdp5_interface *intf; + + struct mdp_irq wb_done; +}; +#define to_mdp5_wb_connector(x) container_of(x, struct mdp5_wb_connector, base) + + +static void mdp5_wb_connector_atomic_commit(struct drm_connector *connector, + struct drm_writeback_job *job); + +static int mdp5_wb_connector_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + + return drm_add_modes_noedid(connector, dev->mode_config.max_width, + dev->mode_config.max_height); +} + +static enum drm_mode_status +mdp5_wb_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct drm_device *dev = connector->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + int w = mode->hdisplay, h = mode->vdisplay; + + if ((w < mode_config->min_width) || (w > mode_config->max_width)) + return MODE_BAD_HVALUE; + + if ((h < mode_config->min_height) || (h > mode_config->max_height)) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + +const struct drm_connector_helper_funcs mdp5_wb_connector_helper_funcs = { + .get_modes = mdp5_wb_connector_get_modes, + .mode_valid = mdp5_wb_connector_mode_valid, + .atomic_commit = mdp5_wb_connector_atomic_commit, +}; + +static enum drm_connector_status +mdp5_wb_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_disconnected; +} + +static void mdp5_wb_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); +} + +static const struct drm_connector_funcs mdp5_wb_connector_funcs = { + .reset = drm_atomic_helper_connector_reset, + .detect = mdp5_wb_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = mdp5_wb_connector_destroy, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int +mdp5_wb_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct msm_drm_private *priv = encoder->dev->dev_private; + struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state); + struct mdp5_wb_connector *mdp5_wb = to_mdp5_wb_connector( + to_wb_connector(conn_state->connector)); + struct drm_framebuffer *fb; + const struct msm_format *format; + const struct mdp_format *mdp_fmt; + struct drm_format_name_buf format_name; + int ret; + + if (!conn_state->writeback_job || !conn_state->writeback_job->fb) + return 0; + + fb = conn_state->writeback_job->fb; + + DBG("wb[%u]: check writeback %ux%u@%s", mdp5_wb->id, + fb->width, fb->height, + drm_get_format_name(fb->format->format, &format_name)); + + format = mdp_get_format(priv->kms, fb->format->format); + if (!format) { + DBG("Invalid pixel format!"); + return -EINVAL; + } + + mdp_fmt = to_mdp_format(format); + if (MDP_FORMAT_IS_YUV(mdp_fmt)) { + switch (mdp_fmt->chroma_sample) { + case CHROMA_420: + case CHROMA_H2V1: + /* supported */ + break; + case CHROMA_H1V2: + default: + DBG("unsupported wb chroma samp=%d\n", + mdp_fmt->chroma_sample); + return -EINVAL; + } + } + + /* TODO I think we would prefer to have proper prepare_fb()/cleanup_fb() + * vfuncs, as with plane.. Also, where to unprepare? + */ + ret = msm_framebuffer_prepare(fb, priv->kms->aspace); + if (ret) + return ret; + + mdp5_cstate->ctl = mdp5_wb->ctl; + mdp5_cstate->pipeline.intf = mdp5_wb->intf; + mdp5_cstate->defer_start = true; + + return 0; +} + +static void +wb_csc_setup(struct mdp5_kms *mdp5_kms, u32 wb_id, struct csc_cfg *csc) +{ + uint32_t i; + uint32_t *matrix; + + if (unlikely(!csc)) + return; + + matrix = csc->matrix; + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_MATRIX_COEFF_0(wb_id), + MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(matrix[0]) | + MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(matrix[1])); + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_MATRIX_COEFF_1(wb_id), + MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(matrix[2]) | + MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(matrix[3])); + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_MATRIX_COEFF_2(wb_id), + MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(matrix[4]) | + MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(matrix[5])); + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_MATRIX_COEFF_3(wb_id), + MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(matrix[6]) | + MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(matrix[7])); + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_MATRIX_COEFF_4(wb_id), + MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(matrix[8])); + + for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { + uint32_t *pre_clamp = csc->pre_clamp; + uint32_t *post_clamp = csc->post_clamp; + + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_COMP_PRECLAMP(wb_id, i), + MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(pre_clamp[2*i+1]) | + MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(pre_clamp[2*i])); + + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_COMP_POSTCLAMP(wb_id, i), + MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(post_clamp[2*i+1]) | + MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(post_clamp[2*i])); + + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_COMP_PREBIAS(wb_id, i), + MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(csc->pre_bias[i])); + + mdp5_write(mdp5_kms, REG_MDP5_WB_CSC_COMP_POSTBIAS(wb_id, i), + MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(csc->post_bias[i])); + } +} + +static void +mdp5_wb_connector_atomic_commit(struct drm_connector *connector, + struct drm_writeback_job *job) +{ + struct msm_drm_private *priv = connector->dev->dev_private; + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); + struct drm_connector_state *conn_state = connector->state; + struct drm_writeback_connector *wb_conn = to_wb_connector(connector); + struct mdp5_crtc_state *mdp5_crtc_state = + to_mdp5_crtc_state(wb_conn->encoder.crtc->state); + struct mdp5_wb_connector *mdp5_wb = to_mdp5_wb_connector(wb_conn); + struct drm_framebuffer *fb = job->fb; + struct drm_format_name_buf format_name; + const struct mdp_format *fmt = + to_mdp_format(mdp_get_format(priv->kms, fb->format->format)); + u32 ystride0, ystride1, outsize; + u32 dst_format, pattern, opmode = 0; + + DBG("wb[%u]: kick writeback %ux%u@%s", mdp5_wb->id, + fb->width, fb->height, + drm_get_format_name(fb->format->format, &format_name)); + + /* queue job before anything that can trigger completion irq */ + drm_writeback_queue_job(wb_conn, job); + conn_state->writeback_job = NULL; + + mdp_irq_register(&mdp5_kms->base, &mdp5_wb->wb_done); + + if (MDP_FORMAT_IS_YUV(fmt)) { + wb_csc_setup(mdp5_kms, mdp5_wb->id, + mdp_get_default_csc_cfg(CSC_RGB2YUV)); + + opmode |= MDP5_WB_DST_OP_MODE_CSC_EN | + MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_RGB) | + MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); + + switch (fmt->chroma_sample) { + case CHROMA_420: + case CHROMA_H2V1: + opmode |= MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN; + break; + case CHROMA_H1V2: + default: + WARN(1, "unsupported wb chroma samp=%d\n", + fmt->chroma_sample); + return; + } + } + + dst_format = MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(fmt->chroma_sample) | + MDP5_WB_DST_FORMAT_WRITE_PLANES(fmt->fetch_type) | + MDP5_WB_DST_FORMAT_DSTC3_OUT(fmt->bpc_a) | + MDP5_WB_DST_FORMAT_DSTC2_OUT(fmt->bpc_r) | + MDP5_WB_DST_FORMAT_DSTC1_OUT(fmt->bpc_b) | + MDP5_WB_DST_FORMAT_DSTC0_OUT(fmt->bpc_g) | + COND(fmt->unpack_tight, MDP5_WB_DST_FORMAT_PACK_TIGHT) | + MDP5_WB_DST_FORMAT_PACK_COUNT(fmt->unpack_count - 1) | + MDP5_WB_DST_FORMAT_DST_BPP(fmt->cpp - 1); + + if (fmt->bpc_a || fmt->alpha_enable) { + dst_format |= MDP5_WB_DST_FORMAT_DSTC3_EN; + if (!fmt->alpha_enable) + dst_format |= MDP5_WB_DST_FORMAT_DST_ALPHA_X; + } + + pattern = MDP5_WB_DST_PACK_PATTERN_ELEMENT3(fmt->unpack[3]) | + MDP5_WB_DST_PACK_PATTERN_ELEMENT2(fmt->unpack[2]) | + MDP5_WB_DST_PACK_PATTERN_ELEMENT1(fmt->unpack[1]) | + MDP5_WB_DST_PACK_PATTERN_ELEMENT0(fmt->unpack[0]); + + ystride0 = MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(fb->pitches[0]) | + MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(fb->pitches[1]); + ystride1 = MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(fb->pitches[2]) | + MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(fb->pitches[3]); + + /* get the output resolution from WB device */ + outsize = MDP5_WB_OUT_SIZE_DST_H(fb->height) | + MDP5_WB_OUT_SIZE_DST_W(fb->width); + + mdp5_write(mdp5_kms, REG_MDP5_WB_ALPHA_X_VALUE(mdp5_wb->id), 0xff); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST_FORMAT(mdp5_wb->id), dst_format); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST_OP_MODE(mdp5_wb->id), opmode); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST_PACK_PATTERN(mdp5_wb->id), pattern); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST_YSTRIDE0(mdp5_wb->id), ystride0); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST_YSTRIDE1(mdp5_wb->id), ystride1); + mdp5_write(mdp5_kms, REG_MDP5_WB_OUT_SIZE(mdp5_wb->id), outsize); + + mdp5_crtc_set_pipeline(wb_conn->encoder.crtc); + + mdp5_write(mdp5_kms, REG_MDP5_WB_DST0_ADDR(mdp5_wb->id), + msm_framebuffer_iova(fb, priv->kms->aspace, 0)); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST1_ADDR(mdp5_wb->id), + msm_framebuffer_iova(fb, priv->kms->aspace, 1)); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST2_ADDR(mdp5_wb->id), + msm_framebuffer_iova(fb, priv->kms->aspace, 2)); + mdp5_write(mdp5_kms, REG_MDP5_WB_DST3_ADDR(mdp5_wb->id), + msm_framebuffer_iova(fb, priv->kms->aspace, 3)); + + /* Notify ctl that wb buffer is ready to trigger start */ + mdp5_ctl_commit(mdp5_wb->ctl, &mdp5_crtc_state->pipeline, + MDP5_CTL_FLUSH_WB, true); + + mdp5_ctl_set_encoder_state(mdp5_wb->ctl, + &mdp5_crtc_state->pipeline, true); +} + +static void mdp5_wb_done_irq(struct mdp_irq *irq, uint32_t irqstatus) +{ + struct mdp5_wb_connector *mdp5_wb = + container_of(irq, struct mdp5_wb_connector, wb_done); + struct mdp5_crtc_state *mdp5_crtc_state = + to_mdp5_crtc_state(mdp5_wb->base.encoder.crtc->state); + struct msm_drm_private *priv = mdp5_wb->base.base.dev->dev_private; + + mdp_irq_unregister(to_mdp_kms(priv->kms), &mdp5_wb->wb_done); + + mdp5_ctl_set_encoder_state(mdp5_wb->ctl, + &mdp5_crtc_state->pipeline, false); + + drm_writeback_signal_completion(&mdp5_wb->base, 0); +} + +static const struct drm_encoder_helper_funcs mdp5_wb_encoder_helper_funcs = { + .atomic_check = mdp5_wb_encoder_atomic_check, +}; + +struct drm_writeback_connector * +mdp5_wb_connector_init(struct drm_device *dev, struct mdp5_ctl *ctl, + unsigned wb_id) +{ + struct drm_connector *connector = NULL; + struct mdp5_wb_connector *mdp5_wb; + + mdp5_wb = kzalloc(sizeof(*mdp5_wb), GFP_KERNEL); + if (!mdp5_wb) + return ERR_PTR(-ENOMEM); + + mdp5_wb->id = wb_id; + mdp5_wb->ctl = ctl; + + /* construct a dummy intf for WB: */ +// TODO un-inline this (and also in interface_init()) + mdp5_wb->intf = kzalloc(sizeof(*mdp5_wb->intf), GFP_KERNEL); + mdp5_wb->intf->num = -1; + mdp5_wb->intf->type = INTF_WB; + mdp5_wb->intf->mode = MDP5_INTF_WB_MODE_LINE; + mdp5_wb->intf->idx = -1; + + mdp5_wb->wb_done.irq = mdp5_wb_done_irq; +// TODO just register for all wb irq's until I figure out the mapping.. + mdp5_wb->wb_done.irqmask = MDP5_IRQ_WB_0_DONE | MDP5_IRQ_WB_1_DONE | MDP5_IRQ_WB_2_DONE; + + connector = &mdp5_wb->base.base; + + drm_connector_helper_add(connector, &mdp5_wb_connector_helper_funcs); + + mdp5_wb->nformats = mdp_get_formats(mdp5_wb->formats, + ARRAY_SIZE(mdp5_wb->formats), false); + + drm_writeback_connector_init(dev, + &mdp5_wb->base, + &mdp5_wb_connector_funcs, + &mdp5_wb_encoder_helper_funcs, + mdp5_wb->formats, + mdp5_wb->nformats); + + connector->interlace_allowed = 0; + connector->doublescan_allowed = 0; + + return &mdp5_wb->base; +} diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7a03a9489708..422f524f7562 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -741,7 +741,7 @@ static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) else intr &= ~mask; - DBG("intr=%x enable=%d", intr, enable); + VERB("intr=%x enable=%d", intr, enable); dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); spin_unlock_irqrestore(&msm_host->intr_lock, flags); @@ -1465,7 +1465,7 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr) dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); spin_unlock_irqrestore(&msm_host->intr_lock, flags); - DBG("isr=0x%x, id=%d", isr, msm_host->id); + VERB("isr=0x%x, id=%d", isr, msm_host->id); if (isr & DSI_IRQ_ERROR) dsi_error(msm_host); -- 2.14.3