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From: Anatolij Gustschin <agust@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] sunxi: video: lcdc: fix HSYNC and VSYNC polarity
Date: Mon, 26 Feb 2018 13:31:53 +0100	[thread overview]
Message-ID: <20180226133153.370c2860@crub> (raw)
In-Reply-To: <20180216131025.shmdl45tnyoextig@flea.lan>

Hi all,

On Fri, 16 Feb 2018 14:10:25 +0100
Maxime Ripard maxime.ripard at bootlin.com wrote:

> Hi,
> 
> On Thu, Feb 15, 2018 at 06:40:53PM +0100, Giulio Benetti wrote:
> > Differently from other Lcd signals, HSYNC and VSYNC signals
> > result inverted if their bits are cleared to 0.
> > 
> > Invert their settings of IO_POL register.
> > 
> > Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
> > ---
> >  drivers/video/sunxi/lcdc.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
> > index 4cb86fb..007057c 100644
> > --- a/drivers/video/sunxi/lcdc.c
> > +++ b/drivers/video/sunxi/lcdc.c
> > @@ -132,9 +132,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
> >  	}
> >  
> >  	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
> > -	if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
> > +	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
> >  		val |= SUNXI_LCDC_TCON_HSYNC_MASK;
> > -	if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
> > +	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
> >  		val |= SUNXI_LCDC_TCON_VSYNC_MASK;
> >    
> 
> As we discussed earlier, I'm really not sure this is worth it. This is
> going to break all the boards out there that store the modeline in the
> environment. And we should fix all the defconfigs (but that's the easy
> part).
> 
> Anatolij, any suggestion?

from the patch description it is not clear to me which problem this
patch tries to solve. AFAICS in the driver code, mode->flags is
initialized either from input data in the EDID blob, sync properties
in "display-timings" device tree node or from the built-in mode
string. I assume the driver already works properly when reading
the sync flags from all these sources. It seems this patch can
also break boards without modeline in the environment. Can't you
adjust sync flags in your CONFIG_VIDEO_LCD_MODE to get the LCD
output working without patching the driver?

Thanks,

Anatolij

  reply	other threads:[~2018-02-26 12:31 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15 17:40 [U-Boot] [PATCH] sunxi: video: lcdc: fix HSYNC and VSYNC polarity Giulio Benetti
2018-02-16 13:10 ` Maxime Ripard
2018-02-26 12:31   ` Anatolij Gustschin [this message]
2018-02-26 13:40     ` Giulio Benetti

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