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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/cnl: Add WaRsDisableCoarsePowerGating
Date: Tue, 27 Feb 2018 15:56:48 -0800	[thread overview]
Message-ID: <20180227235647.GN17137@intel.com> (raw)
In-Reply-To: <20180227012512.6aiqonqq26h2dgud@InViCtUs>

On Mon, Feb 26, 2018 at 05:25:12PM -0800, Radhakrishna Sripada wrote:
> On Thu, Feb 22, 2018 at 12:05:35PM -0800, Rodrigo Vivi wrote:
> > Old Wa added now forever on CNL all steppings.
> > 
> > With CPU P states enabled along with RC6, dispatcher
> > hangs can happen.
> > 
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

merged, thanks

> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  | 5 +++--
> >  drivers/gpu/drm/i915/intel_guc.c | 2 +-
> >  drivers/gpu/drm/i915/intel_pm.c  | 2 +-
> >  3 files changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 82a106b1bdbc..7bbec5546d12 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2788,9 +2788,10 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> >  #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
> >  
> > -/* WaRsDisableCoarsePowerGating:skl,bxt */
> > +/* WaRsDisableCoarsePowerGating:skl,cnl */
> >  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> > -	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> > +	(IS_CANNONLAKE(dev_priv) || \
> > +	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> >  
> >  /*
> >   * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
> > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> > index 21140ccd7a97..e6512cccef75 100644
> > --- a/drivers/gpu/drm/i915/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/intel_guc.c
> > @@ -370,7 +370,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
> >  	u32 action[2];
> >  
> >  	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> > -	/* WaRsDisableCoarsePowerGating:skl,bxt */
> > +	/* WaRsDisableCoarsePowerGating:skl,cnl */
> >  	if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> >  		action[1] = 0;
> >  	else
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 731b3808a62e..c5e495dfa387 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6695,7 +6695,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> >  
> >  	/*
> >  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> > -	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> > +	 * WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
> >  	 */
> >  	if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> >  		I915_WRITE(GEN9_PG_ENABLE, 0);
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2018-02-27 23:56 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-22 20:05 [PATCH] drm/i915/cnl: Add WaRsDisableCoarsePowerGating Rodrigo Vivi
2018-02-22 20:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-02-27  1:25 ` [PATCH] " Radhakrishna Sripada
2018-02-27 23:56   ` Rodrigo Vivi [this message]
2018-02-27 21:31 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-02-27 22:53 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-28  0:15 ` ✗ Fi.CI.IGT: warning " Patchwork

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