From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sn1nam02on0106.outbound.protection.outlook.com ([104.47.36.106]:44032 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1031900AbeCAPXi (ORCPT ); Thu, 1 Mar 2018 10:23:38 -0500 From: Sasha Levin To: "stable@vger.kernel.org" , "stable-commits@vger.kernel.org" CC: Patrice Chotard , Linus Walleij , Sasha Levin Subject: [added to the 4.1 stable tree] pinctrl: st: add irq_request/release_resources callbacks Date: Thu, 1 Mar 2018 15:22:43 +0000 Message-ID: <20180301152116.1486-26-alexander.levin@microsoft.com> References: <20180301152116.1486-1-alexander.levin@microsoft.com> In-Reply-To: <20180301152116.1486-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Patrice Chotard This patch has been added to the 4.1 stable tree. If you have any objections, please let us know. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D [ Upstream commit e855fa9a65c40788b5069abb0d094537daa22e05 ] When using GPIO as IRQ source, the GPIO must be configured in INPUT. Callbacks dedicated for this was missing in pinctrl-st driver. This fix the following kernel error when trying to lock a gpio as IRQ: [ 7.521095] gpio gpiochip7: (PIO11): gpiochip_lock_as_irq: tried to flag= a GPIO set as output for IRQ [ 7.526018] gpio gpiochip7: (PIO11): unable to lock HW IRQ 6 for IRQ [ 7.529405] genirq: Failed to request resources for 0-0053 (irq 81) on i= rqchip GPIO Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-st.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 65bf73b70e34..a02a7caf8d4c 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1348,6 +1348,22 @@ static void st_gpio_irq_unmask(struct irq_data *d) writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); } =20 +static int st_gpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + + st_gpio_direction_input(gc, d->hwirq); + + return gpiochip_lock_as_irq(gc, d->hwirq); +} + +static void st_gpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + + gpiochip_unlock_as_irq(gc, d->hwirq); +} + static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); @@ -1503,12 +1519,14 @@ static struct gpio_chip st_gpio_template =3D { }; =20 static struct irq_chip st_gpio_irqchip =3D { - .name =3D "GPIO", - .irq_disable =3D st_gpio_irq_mask, - .irq_mask =3D st_gpio_irq_mask, - .irq_unmask =3D st_gpio_irq_unmask, - .irq_set_type =3D st_gpio_irq_set_type, - .flags =3D IRQCHIP_SKIP_SET_WAKE, + .name =3D "GPIO", + .irq_request_resources =3D st_gpio_irq_request_resources, + .irq_release_resources =3D st_gpio_irq_release_resources, + .irq_disable =3D st_gpio_irq_mask, + .irq_mask =3D st_gpio_irq_mask, + .irq_unmask =3D st_gpio_irq_unmask, + .irq_set_type =3D st_gpio_irq_set_type, + .flags =3D IRQCHIP_SKIP_SET_WAKE, }; =20 static int st_gpiolib_register_bank(struct st_pinctrl *info, --=20 2.14.1