From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,2/3] dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC From: Vinod Koul Message-Id: <20180302081706.GL15443@localhost> Date: Fri, 2 Mar 2018 13:47:06 +0530 To: Sean Wang Cc: dan.j.williams@intel.com, robh+dt@kernel.org, mark.rutland@arm.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Randy Dunlap , Fengguang Wu , Julia Lawall List-ID: T24gRnJpLCBNYXIgMDIsIDIwMTggYXQgMDI6NDc6NTFQTSArMDgwMCwgU2VhbiBXYW5nIHdyb3Rl Ogo+IEhpLCBWaW5vZAo+IAo+IE9uIFRodSwgMjAxOC0wMy0wMSBhdCAxODoyNiArMDUzMCwgVmlu b2QgS291bCB3cm90ZToKPiA+IE9uIFRodSwgTWFyIDAxLCAyMDE4IGF0IDA2OjI3OjAxUE0gKzA4 MDAsIFNlYW4gV2FuZyB3cm90ZToKPiA+ID4gT24gVGh1LCAyMDE4LTAzLTAxIGF0IDEzOjUzICsw NTMwLCBWaW5vZCBLb3VsIHdyb3RlOgo+ID4gPiA+IE9uIFN1biwgRmViIDE4LCAyMDE4IGF0IDAz OjA4OjMwQU0gKzA4MDAsIHNlYW4ud2FuZ0BtZWRpYXRlay5jb20gd3JvdGU6Cj4gPiA+ID4gCj4g PiA+ID4gPiBAQCAtMCwwICsxLDEwNTQgQEAKPiA+ID4gPiA+ICsvLyBTUERYLUxpY2Vuc2UtSWRl bnRpZmllcjogR1BMLTIuMAo+ID4gPiA+IC8vIENvcHlyaWdodCAuLi4KPiA+ID4gPiAKPiA+ID4g PiBUaGUgY29weXJpZ2h0IGxpbmUgbmVlZHMgdG8gZm9sbG93IFNQRFggdGFnIGxpbmUKPiA+ID4g PiAKPiA+ID4gCj4gPiA+IG9rYXksIEkgd2lsbCBtYWtlIGl0IHJlb3JkZXIgYW5kIGJlIHNvbWV0 aGluZyBsaWtlIHRoYXQKPiA+ID4gCj4gPiA+IC8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBH UEwtMi4wCj4gPiA+IC8qCj4gPiA+ICAqIENvcHlyaWdodCAoYykgMjAxNy0yMDE4IE1lZGlhVGVr IEluYy4KPiA+ID4gICogQXV0aG9yOiBTZWFuIFdhbmcgPHNlYW4ud2FuZ0BtZWRpYXRlay5jb20+ Cj4gPiA+ICAqCj4gPiA+ICAqIERyaXZlciBmb3IgTWVkaWFUZWsgSGlnaC1TcGVlZCBETUEgQ29u dHJvbGxlcgo+ID4gPiAgKgo+ID4gPiAgKi8KPiA+IAo+ID4gSXQgbmVlZHMgdG8gYmU6Cj4gPiAK PiA+IC8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gPiAvLyBDb3B5cmlnaHQg KGMpIDIwMTctMjAxOCBNZWRpYVRlayBJbmMuCj4gPiAKPiA+IC8qCj4gPiAgKiB3aGF0ZXZlciBl bHNlIHlvdSB3YW50Cj4gPiAgKi8KPiA+IAo+ID4gVGhlIGZpcnN0IHR3byBsaW5lcyBhcmUgaW4g Qzk5IHN0eWxlIGNvbW1lbnQgYW5kIG5lZWQgdG8gaGF2ZSBTUERYIHRhZyBhbmQKPiA+IENvcHly aWdodCBpbmZvCj4gCj4gU3VyZSwgSSBjYW4gZG8gaXQgdXNpbmcgQzk5IHN0eWxlIGNvbW1lbnRz IGF0IHRoZSBmaXJzdCB0d28gbGluZXMuCj4gCj4gSW4gYWRkaXRpb24sIEknbSByZWFsbHkgY3Vy aW91cyB3aGVyZSB3ZSBjYW4gZmluZCBhIHJlZmVyZW5jZSB0byB0aGUKPiBydWxlIGFuZCBpZiBp dCAncyBhIHN0cmljdCBydWxlIGZvciBhbGwgdGhlIGRyaXZlcnMuCj4gCj4gQmVjYXVzZSBJJ20g Y29uc2lkZXJpbmcgd2hldGhlciBJIHNob3VsZCB0dXJuIG90aGVyIGRyaXZlciBpbnRvIHVzaW5n Cj4gdGhlIHNhbWUgcnVsZS4KClllcyB0aGF0IHNlZW1zIHRvIGJlIHRoZSBydWxlIG5vdyBodHRw czovL2xrbWwub3JnL2xrbWwvMjAxNy8xMS8yLzcxNQoKPiA+ID4gPiA+ICsjZGVmaW5lIE1US19I U0RNQV9VU0VDX1BPTEwJCTIwCj4gPiA+ID4gPiArI2RlZmluZSBNVEtfSFNETUFfVElNRU9VVF9Q T0xMCQkyMDAwMDAKPiA+ID4gPiA+ICsjZGVmaW5lIE1US19IU0RNQV9ETUFfQlVTV0lEVEhTCQlC SVQoRE1BX1NMQVZFX0JVU1dJRFRIX1VOREVGSU5FRCkKPiA+ID4gPiAKPiA+ID4gPiBVbmRlZmlu ZWQgYnVzd2lkdGg/Pwo+ID4gCj4gPiA/Pwo+IAo+IFNvcnJ5IGZvciBJIGRpZG4ndCBhbnN3ZXIg dGhlIHF1ZXN0aW9uIGluIHRoZSBzaG9ydCB0aW1lLgo+IAo+IEFmdGVyIHNwZW5kaW5nIHNvbWUg dGltZSBvbiBhIGNvbmZpcm1hdGlvbiB3aXRoIGRlc2lnbiwgaXQgaXMKPiBETUFfU0xBVkVfQlVT V0lEVEhfNF9CWVRFUyBhbmQgbm90IGJlIGNvbmZpZ3VyYWJsZS4gCgpUaGVuIGl0IHNob3VsZCBi ZSBETUFfU0xBVkVfQlVTV0lEVEhfNF9CWVRFUyBhbmQgbm90CkRNQV9TTEFWRV9CVVNXSURUSF9V TkRFRklORUQuLi4KCj4gPiA+ID4gc2hvdWxkbid0IHdlIGNoZWNrIGlmIG5leHQgaXMgaW4gcmFu Z2UsIHdlIGNhbiBjcmFzaCBpZiB3ZSBnZXQgYmFkIHZhbHVlCj4gPiA+ID4gZnJvbSBoYXJkd2Fy ZS4uCj4gPiA+IAo+ID4gPiBva2F5LCB0aGVyZSBhcmUgY2hlY2tzIGZvciBuZXh0IHdpdGggZGRv bmUgYml0IGNoZWNrIGFuZCBudWxsIGNoZWNrIGluCj4gPiA+IHRoZSBjb3JyZXNwb25kaW5nIGRl c2NyaXB0b3IgYXMgdGhlIGZvbGxvd2luZy4KPiA+IAo+ID4gd2hhdCBpZiB5b3UgZ2V0IGJhZCBu ZXh0IHZhbHVlCj4gPiAKPiAKPiBuZXh0IGlzIG5vdCBoYXJkd2FyZSB2YWx1ZS4gaXQncyBtYWlu dGFpbmVkIGJ5IHNvZnR3YXJlIHdoaWNoIGlzIGFsd2F5cwo+IGJldHdlZW4gMCB0byBNVEtfRE1B X1NJWkUgLSAxLCBhbmQgZGVmaW5pdGVseSBkb2Vzbid0IGdldCBhIGJhZCB2YWx1ZS4KPiAKPiA+ ID4gCj4gPiA+ID4gPiArCQlyeGQgPSAmcGMtPnJpbmcucnhkW25leHRdOwo+ID4gCj4gPiByZXN1 bHRpbmcgaW4gYmFkIHJlZiBoZXJlCj4gCj4gcnhkIGlzIGFsc28gZGVmaW5pdGVseSBhIGdvb2Qg cmVmCgpub3QgaWYgbmV4dCBpcyBvdXQgb2YgcmFuZ2UsIHNheSB5b3UgcmVhZCAtMSBvciAyMDAw MDA/Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Subject: Re: [PATCH v5 2/3] dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC Date: Fri, 2 Mar 2018 13:47:06 +0530 Message-ID: <20180302081706.GL15443@localhost> References: <20180301082329.GD15443@localhost> <1519900021.8089.136.camel@mtkswgap22> <20180301125649.GH15443@localhost> <1519973271.8089.166.camel@mtkswgap22> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1519973271.8089.166.camel@mtkswgap22> Sender: linux-kernel-owner@vger.kernel.org To: Sean Wang Cc: dan.j.williams@intel.com, robh+dt@kernel.org, mark.rutland@arm.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Randy Dunlap , Fengguang Wu , Julia Lawall List-Id: linux-mediatek@lists.infradead.org On Fri, Mar 02, 2018 at 02:47:51PM +0800, Sean Wang wrote: > Hi, Vinod > > On Thu, 2018-03-01 at 18:26 +0530, Vinod Koul wrote: > > On Thu, Mar 01, 2018 at 06:27:01PM +0800, Sean Wang wrote: > > > On Thu, 2018-03-01 at 13:53 +0530, Vinod Koul wrote: > > > > On Sun, Feb 18, 2018 at 03:08:30AM +0800, sean.wang@mediatek.com wrote: > > > > > > > > > @@ -0,0 +1,1054 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > // Copyright ... > > > > > > > > The copyright line needs to follow SPDX tag line > > > > > > > > > > okay, I will make it reorder and be something like that > > > > > > // SPDX-License-Identifier: GPL-2.0 > > > /* > > > * Copyright (c) 2017-2018 MediaTek Inc. > > > * Author: Sean Wang > > > * > > > * Driver for MediaTek High-Speed DMA Controller > > > * > > > */ > > > > It needs to be: > > > > // SPDX-License-Identifier: GPL-2.0 > > // Copyright (c) 2017-2018 MediaTek Inc. > > > > /* > > * whatever else you want > > */ > > > > The first two lines are in C99 style comment and need to have SPDX tag and > > Copyright info > > Sure, I can do it using C99 style comments at the first two lines. > > In addition, I'm really curious where we can find a reference to the > rule and if it 's a strict rule for all the drivers. > > Because I'm considering whether I should turn other driver into using > the same rule. Yes that seems to be the rule now https://lkml.org/lkml/2017/11/2/715 > > > > > +#define MTK_HSDMA_USEC_POLL 20 > > > > > +#define MTK_HSDMA_TIMEOUT_POLL 200000 > > > > > +#define MTK_HSDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) > > > > > > > > Undefined buswidth?? > > > > ?? > > Sorry for I didn't answer the question in the short time. > > After spending some time on a confirmation with design, it is > DMA_SLAVE_BUSWIDTH_4_BYTES and not be configurable. Then it should be DMA_SLAVE_BUSWIDTH_4_BYTES and not DMA_SLAVE_BUSWIDTH_UNDEFINED... > > > > shouldn't we check if next is in range, we can crash if we get bad value > > > > from hardware.. > > > > > > okay, there are checks for next with ddone bit check and null check in > > > the corresponding descriptor as the following. > > > > what if you get bad next value > > > > next is not hardware value. it's maintained by software which is always > between 0 to MTK_DMA_SIZE - 1, and definitely doesn't get a bad value. > > > > > > > > > + rxd = &pc->ring.rxd[next]; > > > > resulting in bad ref here > > rxd is also definitely a good ref not if next is out of range, say you read -1 or 200000? -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Fri, 2 Mar 2018 13:47:06 +0530 Subject: [PATCH v5 2/3] dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC In-Reply-To: <1519973271.8089.166.camel@mtkswgap22> References: <20180301082329.GD15443@localhost> <1519900021.8089.136.camel@mtkswgap22> <20180301125649.GH15443@localhost> <1519973271.8089.166.camel@mtkswgap22> Message-ID: <20180302081706.GL15443@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Mar 02, 2018 at 02:47:51PM +0800, Sean Wang wrote: > Hi, Vinod > > On Thu, 2018-03-01 at 18:26 +0530, Vinod Koul wrote: > > On Thu, Mar 01, 2018 at 06:27:01PM +0800, Sean Wang wrote: > > > On Thu, 2018-03-01 at 13:53 +0530, Vinod Koul wrote: > > > > On Sun, Feb 18, 2018 at 03:08:30AM +0800, sean.wang at mediatek.com wrote: > > > > > > > > > @@ -0,0 +1,1054 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > // Copyright ... > > > > > > > > The copyright line needs to follow SPDX tag line > > > > > > > > > > okay, I will make it reorder and be something like that > > > > > > // SPDX-License-Identifier: GPL-2.0 > > > /* > > > * Copyright (c) 2017-2018 MediaTek Inc. > > > * Author: Sean Wang > > > * > > > * Driver for MediaTek High-Speed DMA Controller > > > * > > > */ > > > > It needs to be: > > > > // SPDX-License-Identifier: GPL-2.0 > > // Copyright (c) 2017-2018 MediaTek Inc. > > > > /* > > * whatever else you want > > */ > > > > The first two lines are in C99 style comment and need to have SPDX tag and > > Copyright info > > Sure, I can do it using C99 style comments at the first two lines. > > In addition, I'm really curious where we can find a reference to the > rule and if it 's a strict rule for all the drivers. > > Because I'm considering whether I should turn other driver into using > the same rule. Yes that seems to be the rule now https://lkml.org/lkml/2017/11/2/715 > > > > > +#define MTK_HSDMA_USEC_POLL 20 > > > > > +#define MTK_HSDMA_TIMEOUT_POLL 200000 > > > > > +#define MTK_HSDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) > > > > > > > > Undefined buswidth?? > > > > ?? > > Sorry for I didn't answer the question in the short time. > > After spending some time on a confirmation with design, it is > DMA_SLAVE_BUSWIDTH_4_BYTES and not be configurable. Then it should be DMA_SLAVE_BUSWIDTH_4_BYTES and not DMA_SLAVE_BUSWIDTH_UNDEFINED... > > > > shouldn't we check if next is in range, we can crash if we get bad value > > > > from hardware.. > > > > > > okay, there are checks for next with ddone bit check and null check in > > > the corresponding descriptor as the following. > > > > what if you get bad next value > > > > next is not hardware value. it's maintained by software which is always > between 0 to MTK_DMA_SIZE - 1, and definitely doesn't get a bad value. > > > > > > > > > + rxd = &pc->ring.rxd[next]; > > > > resulting in bad ref here > > rxd is also definitely a good ref not if next is out of range, say you read -1 or 200000? -- ~Vinod