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Thu, 8 Mar 2018 02:08:38 -0500 Received: from mail-bn3nam01on0138.outbound.protection.outlook.com ([104.47.33.138]:1475 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755009AbeCHE4R (ORCPT ); Wed, 7 Mar 2018 23:56:17 -0500 From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: Geert Uytterhoeven , Mark Brown , Sasha Levin Subject: [PATCH AUTOSEL for 4.15 17/78] spi: sh-msiof: Avoid writing to registers from spi_master.setup() Thread-Topic: [PATCH AUTOSEL for 4.15 17/78] spi: sh-msiof: Avoid writing to registers from spi_master.setup() Thread-Index: AQHTtpnFhHMHnLWLZ0OiZpRKfpEY9A== Date: Thu, 8 Mar 2018 04:56:08 +0000 Message-ID: <20180308045525.7662-17-alexander.levin@microsoft.com> References: <20180308045525.7662-1-alexander.levin@microsoft.com> In-Reply-To: <20180308045525.7662-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB1111;20:wPyRiG2hdrrTFC/ACWV86Ccolnq5aqmZeshJfU8CbDzUACC6SRYGZxDK2krAJrEuWRm8o3oaiLg86lYkMWVnNK4X2LPpD5oioDEhSKU9oacVKWawHfScRahef0TTRpBTAQuKVzgdwTVdYjOuBmBtp+LmumG3nKkF4c/zthddqbI= x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 7995b04d-b7a1-4785-691f-08d584b0eaa8 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB1111; 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x-microsoft-antispam-message-info: 6Hmrg7U7DxIguYGSegcl22t4ic8lI3ud0yIl8lv8WiiwJjs0B+Ke0kcl1DWujuByggGkGUkGUplsEBIjo/UnBy42nMDYSC07IaJVsuwuxj3apGGSctqH0TAckh2R6MZ8ZpRWpo+HWSOpYX1OhqX6ysPHbD+dPCHGx+xnC/n2jYLjETPgU/+GgAniaN5LBvQ3zKaxBniCFXfH5pLfTIz/2av2SC2ntyu82DIq55Np5i2jh6OexnvyksEAroltgG/eXYTovKdaF1kexvx+dHy0zg2vexGd0CG+6lCyEcFCuVWYJyhdpMGyg7WX7G/WZk99qQhmLWNDFm8biZh2C/VAwQ== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7995b04d-b7a1-4785-691f-08d584b0eaa8 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2018 04:56:08.4538 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB1111 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Geert Uytterhoeven [ Upstream commit 7ff0b53c4051145d1cf992d2f60987e6447eed4f ] The spi_master.setup() callback must not change configuration registers, as that could corrupt I/O that is in progress for other SPI slaves. The only exception is the configuration of the native chip select polarity in SPI master mode, as a wrong chip select polarity will cause havoc during all future transfers to any other SPI slave. Hence stop writing to registers in sh_msiof_spi_setup(), unless it is the first call for a controller using a native chip select, or unless native chip select polarity has changed (note that you'll loose anyway if I/O is in progress). Even then, only do what is strictly necessary, instead of calling sh_msiof_spi_set_pin_regs(). Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-sh-msiof.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index fcd261f98b9f..bf34e9b238af 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -55,6 +55,8 @@ struct sh_msiof_spi_priv { void *rx_dma_page; dma_addr_t tx_dma_addr; dma_addr_t rx_dma_addr; + bool native_cs_inited; + bool native_cs_high; bool slave_aborted; }; =20 @@ -528,8 +530,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi) { struct device_node *np =3D spi->master->dev.of_node; struct sh_msiof_spi_priv *p =3D spi_master_get_devdata(spi->master); - - pm_runtime_get_sync(&p->pdev->dev); + u32 clr, set, tmp; =20 if (!np) { /* @@ -539,19 +540,31 @@ static int sh_msiof_spi_setup(struct spi_device *spi) spi->cs_gpio =3D (uintptr_t)spi->controller_data; } =20 - /* Configure pins before deasserting CS */ - sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), - !!(spi->mode & SPI_CPHA), - !!(spi->mode & SPI_3WIRE), - !!(spi->mode & SPI_LSB_FIRST), - !!(spi->mode & SPI_CS_HIGH)); - - if (spi->cs_gpio >=3D 0) + if (spi->cs_gpio >=3D 0) { gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); + return 0; + } =20 + if (spi_controller_is_slave(p->master)) + return 0; =20 - pm_runtime_put(&p->pdev->dev); + if (p->native_cs_inited && + (p->native_cs_high =3D=3D !!(spi->mode & SPI_CS_HIGH))) + return 0; =20 + /* Configure native chip select mode/polarity early */ + clr =3D MDR1_SYNCMD_MASK; + set =3D MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI; + if (spi->mode & SPI_CS_HIGH) + clr |=3D BIT(MDR1_SYNCAC_SHIFT); + else + set |=3D BIT(MDR1_SYNCAC_SHIFT); + pm_runtime_get_sync(&p->pdev->dev); + tmp =3D sh_msiof_read(p, TMDR1) & ~clr; + sh_msiof_write(p, TMDR1, tmp | set); + pm_runtime_put(&p->pdev->dev); + p->native_cs_high =3D spi->mode & SPI_CS_HIGH; + p->native_cs_inited =3D true; return 0; } =20 --=20 2.14.1