From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v3] dmaengine: mv_xor_v2: Fix clock resource by adding a register clock From: Vinod Koul Message-Id: <20180311150423.GC15443@localhost> Date: Sun, 11 Mar 2018 20:34:23 +0530 To: Gregory CLEMENT Cc: dmaengine@vger.kernel.org, Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Antoine Tenart , =?iso-8859-1?Q?Miqu=E8l?= Raynal , Nadav Haklai , Shadi Ammouri , Omri Itach , Hanna Hawa , Igal Liberman , Marcin Wojtas List-ID: T24gV2VkLCBNYXIgMDcsIDIwMTggYXQgMDQ6NDA6MTBQTSArMDEwMCwgR3JlZ29yeSBDTEVNRU5U IHdyb3RlOgo+IE9uIHRoZSBDUDExMCBjb21wb25lbnRzIHdoaWNoIGFyZSBwcmVzZW50IG9uIHRo ZSBBcm1hZGEgN0svOEsgU29DIHdlIG5lZWQKPiB0byBleHBsaWNpdGx5IGVuYWJsZSB0aGUgY2xv Y2sgZm9yIHRoZSByZWdpc3RlcnMuIEhvd2V2ZXIgaXQgaXMgbm90Cj4gbmVlZGVkIGZvciB0aGUg QVA4eHggY29tcG9uZW50LCB0aGF0J3Mgd2h5IHRoaXMgY2xvY2sgaXMgb3B0aW9uYWwuCj4gCj4g V2l0aCB0aGlzIHBhdGNoIGJvdGggY2xvY2sgaGF2ZSBub3cgYSBuYW1lLCBidXQgaW4gb3JkZXIg dG8gYmUgYmFja3dhcmQKPiBjb21wYXRpYmxlLCB0aGUgbmFtZSBvZiB0aGUgZmlyc3QgY2xvY2sg aXMgbm90IHVzZWQuIEl0IGFsbG93cyB0byBzdGlsbAo+IHVzZSB0aGlzIGNsb2NrIHdpdGggYSBk ZXZpY2UgdHJlZSB1c2luZyB0aGUgb2xkIGJpbmRpbmcuCgpBcHBsaWVkLCB0aGFua3MK From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Sun, 11 Mar 2018 20:34:23 +0530 Subject: [PATCH v3] dmaengine: mv_xor_v2: Fix clock resource by adding a register clock In-Reply-To: <20180307154010.10430-1-gregory.clement@bootlin.com> References: <20180307154010.10430-1-gregory.clement@bootlin.com> Message-ID: <20180311150423.GC15443@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Mar 07, 2018 at 04:40:10PM +0100, Gregory CLEMENT wrote: > On the CP110 components which are present on the Armada 7K/8K SoC we need > to explicitly enable the clock for the registers. However it is not > needed for the AP8xx component, that's why this clock is optional. > > With this patch both clock have now a name, but in order to be backward > compatible, the name of the first clock is not used. It allows to still > use this clock with a device tree using the old binding. Applied, thanks -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Subject: Re: [PATCH v3] dmaengine: mv_xor_v2: Fix clock resource by adding a register clock Date: Sun, 11 Mar 2018 20:34:23 +0530 Message-ID: <20180311150423.GC15443@localhost> References: <20180307154010.10430-1-gregory.clement@bootlin.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20180307154010.10430-1-gregory.clement@bootlin.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Gregory CLEMENT Cc: Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Antoine Tenart , Hanna Hawa , Omri Itach , Nadav Haklai , Rob Herring , Shadi Ammouri , Igal Liberman , Thomas Petazzoni , =?iso-8859-1?Q?Miqu=E8l?= Raynal , dmaengine@vger.kernel.org, Marcin Wojtas , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org On Wed, Mar 07, 2018 at 04:40:10PM +0100, Gregory CLEMENT wrote: > On the CP110 components which are present on the Armada 7K/8K SoC we need > to explicitly enable the clock for the registers. However it is not > needed for the AP8xx component, that's why this clock is optional. > > With this patch both clock have now a name, but in order to be backward > compatible, the name of the first clock is not used. It allows to still > use this clock with a device tree using the old binding. Applied, thanks -- ~Vinod