diff for duplicates of <20180312141224.11907-4-rnayak@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 27c8dce..1f4a611 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -63,7 +63,7 @@ index 000000000000..32f8561deb43 + + chosen { }; + -+ memory@80000000 { ++ memory at 80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; @@ -73,7 +73,7 @@ index 000000000000..32f8561deb43 + #address-cells = <2>; + #size-cells = <0>; + -+ CPU0: cpu@0 { ++ CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; @@ -88,7 +88,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU1: cpu@100 { ++ CPU1: cpu at 100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; @@ -100,7 +100,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU2: cpu@200 { ++ CPU2: cpu at 200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; @@ -112,7 +112,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU3: cpu@300 { ++ CPU3: cpu at 300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; @@ -124,7 +124,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU4: cpu@400 { ++ CPU4: cpu at 400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; @@ -136,7 +136,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU5: cpu@500 { ++ CPU5: cpu at 500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; @@ -148,7 +148,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU6: cpu@600 { ++ CPU6: cpu at 600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; @@ -160,7 +160,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ CPU7: cpu@700 { ++ CPU7: cpu at 700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; @@ -206,7 +206,7 @@ index 000000000000..32f8561deb43 + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + -+ intc: interrupt-controller@17a00000 { ++ intc: interrupt-controller at 17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; @@ -217,7 +217,7 @@ index 000000000000..32f8561deb43 + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + -+ gic-its@17a40000 { ++ gic-its at 17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; @@ -226,7 +226,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ gcc: clock-controller@100000 { ++ gcc: clock-controller at 100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; @@ -234,7 +234,7 @@ index 000000000000..32f8561deb43 + #power-domain-cells = <1>; + }; + -+ tlmm: pinctrl@3400000 { ++ tlmm: pinctrl at 3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -244,14 +244,14 @@ index 000000000000..32f8561deb43 + #interrupt-cells = <2>; + }; + -+ timer@17c90000 { ++ timer at 17c90000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c90000 0x1000>; + -+ frame@17ca0000 { ++ frame at 17ca0000 { + frame-number = <0>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -259,42 +259,42 @@ index 000000000000..32f8561deb43 + <0x17cb0000 0x1000>; + }; + -+ frame@17cc0000 { ++ frame at 17cc0000 { + frame-number = <1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cc0000 0x1000>; + status = "disabled"; + }; + -+ frame@17cd0000 { ++ frame at 17cd0000 { + frame-number = <2>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cd0000 0x1000>; + status = "disabled"; + }; + -+ frame@17ce0000 { ++ frame at 17ce0000 { + frame-number = <3>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17ce0000 0x1000>; + status = "disabled"; + }; + -+ frame@17cf0000 { ++ frame at 17cf0000 { + frame-number = <4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cf0000 0x1000>; + status = "disabled"; + }; + -+ frame@17d00000 { ++ frame at 17d00000 { + frame-number = <5>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d00000 0x1000>; + status = "disabled"; + }; + -+ frame@17d10000 { ++ frame at 17d10000 { + frame-number = <6>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d10000 0x1000>; @@ -302,7 +302,7 @@ index 000000000000..32f8561deb43 + }; + }; + -+ spmi_bus: spmi@c440000 { ++ spmi_bus: spmi at c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, diff --git a/a/content_digest b/N1/content_digest index 439daed..be59b81 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,8 @@ "ref\020180312141224.11907-1-rnayak@codeaurora.org\0" - "From\0Rajendra Nayak <rnayak@codeaurora.org>\0" + "From\0rnayak@codeaurora.org (Rajendra Nayak)\0" "Subject\0[PATCH v7 3/3] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP\0" "Date\0Mon, 12 Mar 2018 19:42:24 +0530\0" - "To\0andy.gross@linaro.org\0" - "Cc\0devicetree@vger.kernel.org" - linux-arm-msm@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - swboyd@chromium.org - evgreen@chromium.org - bjorn.andersson@linaro.org - dianders@chromium.org - marc.zyngier@arm.com - " Rajendra Nayak <rnayak@codeaurora.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files\n" @@ -80,7 +70,7 @@ "+\n" "+\tchosen { };\n" "+\n" - "+\tmemory@80000000 {\n" + "+\tmemory at 80000000 {\n" "+\t\tdevice_type = \"memory\";\n" "+\t\t/* We expect the bootloader to fill in the size */\n" "+\t\treg = <0 0x80000000 0 0>;\n" @@ -90,7 +80,7 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tCPU0: cpu@0 {\n" + "+\t\tCPU0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x0>;\n" @@ -105,7 +95,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU1: cpu@100 {\n" + "+\t\tCPU1: cpu at 100 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x100>;\n" @@ -117,7 +107,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU2: cpu@200 {\n" + "+\t\tCPU2: cpu at 200 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x200>;\n" @@ -129,7 +119,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU3: cpu@300 {\n" + "+\t\tCPU3: cpu at 300 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x300>;\n" @@ -141,7 +131,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU4: cpu@400 {\n" + "+\t\tCPU4: cpu at 400 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x400>;\n" @@ -153,7 +143,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU5: cpu@500 {\n" + "+\t\tCPU5: cpu at 500 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x500>;\n" @@ -165,7 +155,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU6: cpu@600 {\n" + "+\t\tCPU6: cpu at 600 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x600>;\n" @@ -177,7 +167,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU7: cpu@700 {\n" + "+\t\tCPU7: cpu at 700 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo385\";\n" "+\t\t\treg = <0x0 0x700>;\n" @@ -223,7 +213,7 @@ "+\t\tranges = <0 0 0 0xffffffff>;\n" "+\t\tcompatible = \"simple-bus\";\n" "+\n" - "+\t\tintc: interrupt-controller@17a00000 {\n" + "+\t\tintc: interrupt-controller at 17a00000 {\n" "+\t\t\tcompatible = \"arm,gic-v3\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" @@ -234,7 +224,7 @@ "+\t\t\t <0x17a60000 0x100000>; /* GICR * 8 */\n" "+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "+\n" - "+\t\t\tgic-its@17a40000 {\n" + "+\t\t\tgic-its at 17a40000 {\n" "+\t\t\t\tcompatible = \"arm,gic-v3-its\";\n" "+\t\t\t\tmsi-controller;\n" "+\t\t\t\t#msi-cells = <1>;\n" @@ -243,7 +233,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tgcc: clock-controller@100000 {\n" + "+\t\tgcc: clock-controller at 100000 {\n" "+\t\t\tcompatible = \"qcom,gcc-sdm845\";\n" "+\t\t\treg = <0x100000 0x1f0000>;\n" "+\t\t\t#clock-cells = <1>;\n" @@ -251,7 +241,7 @@ "+\t\t\t#power-domain-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\ttlmm: pinctrl@3400000 {\n" + "+\t\ttlmm: pinctrl at 3400000 {\n" "+\t\t\tcompatible = \"qcom,sdm845-pinctrl\";\n" "+\t\t\treg = <0x03400000 0xc00000>;\n" "+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -261,14 +251,14 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\ttimer@17c90000 {\n" + "+\t\ttimer at 17c90000 {\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" "+\t\t\tcompatible = \"arm,armv7-timer-mem\";\n" "+\t\t\treg = <0x17c90000 0x1000>;\n" "+\n" - "+\t\t\tframe@17ca0000 {\n" + "+\t\t\tframe at 17ca0000 {\n" "+\t\t\t\tframe-number = <0>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,\n" "+\t\t\t\t\t <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -276,42 +266,42 @@ "+\t\t\t\t <0x17cb0000 0x1000>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17cc0000 {\n" + "+\t\t\tframe at 17cc0000 {\n" "+\t\t\t\tframe-number = <1>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17cc0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17cd0000 {\n" + "+\t\t\tframe at 17cd0000 {\n" "+\t\t\t\tframe-number = <2>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17cd0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17ce0000 {\n" + "+\t\t\tframe at 17ce0000 {\n" "+\t\t\t\tframe-number = <3>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17ce0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17cf0000 {\n" + "+\t\t\tframe at 17cf0000 {\n" "+\t\t\t\tframe-number = <4>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17cf0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17d00000 {\n" + "+\t\t\tframe at 17d00000 {\n" "+\t\t\t\tframe-number = <5>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17d00000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@17d10000 {\n" + "+\t\t\tframe at 17d10000 {\n" "+\t\t\t\tframe-number = <6>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x17d10000 0x1000>;\n" @@ -319,7 +309,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tspmi_bus: spmi@c440000 {\n" + "+\t\tspmi_bus: spmi at c440000 {\n" "+\t\t\tcompatible = \"qcom,spmi-pmic-arb\";\n" "+\t\t\treg = <0xc440000 0x1100>,\n" "+\t\t\t <0xc600000 0x2000000>,\n" @@ -343,4 +333,4 @@ "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member\n" of Code Aurora Forum, hosted by The Linux Foundation -878869fc38ce7761377bf15bffcc4ec6e2354f12530472923509872468cc11bf +db238de40723d6eec1676e9b19b959496a414f6cb0e79fb8ff5cf43ad6660448
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