From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Date: Fri, 16 Mar 2018 12:51:52 -0600 Message-ID: <20180316185152.32020-3-jcrouse@codeaurora.org> References: <20180316185152.32020-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180316185152.32020-1-jcrouse@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: freedreno@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, dri-devel@lists.freedesktop.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-arm-msm@vger.kernel.org QWRkIHRoZSBub2RlcyB0byBkZXNjcmliZSB0aGUgQWRyZW5vIEdQVSBhbmQgR01VIGRldmljZXMu CgpTaWduZWQtb2ZmLWJ5OiBKb3JkYW4gQ3JvdXNlIDxqY3JvdXNlQGNvZGVhdXJvcmEub3JnPgot LS0KIGFyY2gvYXJtNjQvYm9vdC9kdHMvcWNvbS9zZG04NDUuZHRzaSB8IDExOSArKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDExOSBpbnNlcnRpb25z KCspCgpkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpIGIv YXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpCmluZGV4IDE2YjVmMzU2ZWM5Ni4u ODU0ZGE2NjA0NDE3IDEwMDY0NAotLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL3Fjb20vc2RtODQ1 LmR0c2kKKysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpCkBAIC0zMTIs NCArMzEyLDEyMyBAQAogCQkJfTsKIAkJfTsKIAl9OworCisJYWRyZW5vX3NtbXU6IGFybSxzbW11 LWFkcmVub0A1MDQwMDAwIHsKKwkJY29tcGF0aWJsZSA9ICJxY29tLG1zbTg5OTYtc21tdS12MiI7 CisJCXJlZyA9IDwweDUwNDAwMDAgMHgxMDAwMD47CisJCSNpb21tdS1jZWxscyA9IDwxPjsKKwkJ I2dsb2JhbC1pbnRlcnJ1cHRzID0gPDI+OworCQlpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMjI5IElS UV9UWVBFX0xFVkVMX0hJR0g+LAorCQkJICAgICA8R0lDX1NQSSAyMzEgSVJRX1RZUEVfTEVWRUxf SElHSD4sCisJCQkgICAgIDxHSUNfU1BJIDM2NCBJUlFfVFlQRV9FREdFX1JJU0lORz4sCisJCQkg ICAgIDxHSUNfU1BJIDM2NSBJUlFfVFlQRV9FREdFX1JJU0lORz4sCisJCQkgICAgIDxHSUNfU1BJ IDM2NiBJUlFfVFlQRV9FREdFX1JJU0lORz4sCisJCQkgICAgIDxHSUNfU1BJIDM2NyBJUlFfVFlQ RV9FREdFX1JJU0lORz4sCisJCQkgICAgIDxHSUNfU1BJIDM2OCBJUlFfVFlQRV9FREdFX1JJU0lO Rz4sCisJCQkgICAgIDxHSUNfU1BJIDM2OSBJUlFfVFlQRV9FREdFX1JJU0lORz4sCisJCQkgICAg IDxHSUNfU1BJIDM3MCBJUlFfVFlQRV9FREdFX1JJU0lORz4sCisJCQkgICAgIDxHSUNfU1BJIDM3 MSBJUlFfVFlQRV9FREdFX1JJU0lORz47CisJCWNsb2NrcyA9IDwmY2xvY2tfZ2NjIEdDQ19HUFVf TUVNTk9DX0dGWF9DTEs+LAorCQkJIDwmY2xvY2tfZ2NjIEdDQ19HUFVfQ0ZHX0FIQl9DTEs+Owor CQljbG9jay1uYW1lcyA9ICJidXMiLCAiaWZhY2UiOworCisJCXBvd2VyLWRvbWFpbnMgPSA8JmNs b2NrX2dwdWNjIEdQVV9DWF9HRFNDPjsKKwl9OworCisJZ3B1X29wcF90YWJsZTogYWRyZW5vLW9w cC10YWJsZSB7CisJCWNvbXBhdGlibGUgPSAib3BlcmF0aW5nLXBvaW50cy12MiI7CisKKwkJb3Bw LTcxMDAwMDAwMCB7CisJCQlvcHAtaHogPSAvYml0cy8gNjQgPDcxMDAwMDAwMD47CisJCQlxY29t LGxldmVsID0gPDQxNj47CisJCX07CisKKwkJb3BwLTY3NTAwMDAwMCB7CisJCQlvcHAtaHogPSAv Yml0cy8gNjQgPDY3NTAwMDAwMD47CisJCQlxY29tLGxldmVsID0gPDM4ND47CisJCX07CisKKwkJ b3BwLTU5NjAwMDAwMCB7CisJCQlvcHAtaHogPSAvYml0cy8gNjQgPDU5NjAwMDAwMD47CisJCQlx Y29tLGxldmVsID0gPDMyMD47CisJCX07CisKKwkJb3BwLTUyMDAwMDAwMCB7CisJCQlvcHAtaHog PSAvYml0cy8gNjQgPDUyMDAwMDAwMD47CisJCQlxY29tLGxldmVsID0gPDI1Nj47CisJCX07CisK KwkJb3BwLTQxNDAwMDAwMCB7CisJCQlvcHAtaHogPSAvYml0cy8gNjQgPDQxNDAwMDAwMD47CisJ CQlxY29tLGxldmVsID0gPDE5Mj47CisJCX07CisKKwkJb3BwLTM0MjAwMDAwMCB7CisJCQlvcHAt aHogPSAvYml0cy8gNjQgPDM0MjAwMDAwMD47CisJCQlxY29tLGxldmVsID0gPDEyOD47CisJCX07 CisKKwkJb3BwLTI1NzAwMDAwMCB7CisJCQlvcHAtaHogPSAvYml0cy8gNjQgPDI1NzAwMDAwMD47 CisJCQlxY29tLGxldmVsID0gPDY0PjsKKwkJfTsKKwl9OworCisJZ3B1QDUwMDAwMDAgeworCQlj b21wYXRpYmxlID0gInFjb20sYWRyZW5vLTYzMC4yIiwgInFjb20sYWRyZW5vIjsKKwkJI3N0cmVh bS1pZC1jZWxscyA9IDwxNj47CisKKwkJcmVnID0gPDB4NTAwMDAwMCAweDQwMDAwPjsKKwkJcmVn LW5hbWVzID0gImtnc2xfM2QwX3JlZ19tZW1vcnkiOworCisJCS8qCisJCSAqIExvb2sgbWEsIG5v IGNsb2NrcyEgVGhlIEdQVSBjbG9ja3MgYW5kIHBvd2VyIGFyZSBjb250cm9sbGVkCisJCSAqIGVu dGlyZWx5IGJ5IHRoZSBHTVUKKwkJICovCisKKwkJaW50ZXJydXB0cyA9IDwwIDMwMCAwPjsKKwkJ aW50ZXJydXB0LW5hbWVzID0gImtnc2xfM2QwX2lycSI7CisKKwkJaW9tbXVzID0gPCZhZHJlbm9f c21tdSAwPjsKKworCQlvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZncHVfb3BwX3RhYmxlPjsKKwor CQlnbXUgPSA8JmdtdT47CisJfTsKKworCWdtdV9vcHBfdGFibGU6IGFkcmVuby1nbXUtb3BwLXRh YmxlIHsKKwkJY29tcGF0aWJsZSA9ICJvcGVyYXRpbmctcG9pbnRzLXYyIjsKKworCQlvcHAtNDAw MDAwMDAwIHsKKwkJCW9wcC1oeiA9IC9iaXRzLyA2NCA8NDAwMDAwMDAwPjsKKwkJCXFjb20sbGV2 ZWwgPSA8MTI4PjsKKwkJfTsKKworCQlvcHAtMjAwMDAwMDAwIHsKKwkJCW9wcC1oeiA9IC9iaXRz LyA2NCA8MjAwMDAwMDAwPjsKKwkJCXFjb20sbGV2ZWwgPSA8NDg+OworCQl9OworCX07CisKKwln bXU6IGdtdUA1MDZhMDAwIHsKKwkJY29tcGF0aWJsZT0icWNvbSxhZHJlbm8tZ211IjsKKworCQly ZWcgPSA8MHg1MDZhMDAwIDB4MzAwMDA+LCA8MHhiMjAwMDAwIDB4MzAwMDAwPjsKKwkJcmVnLW5h bWVzID0gImdtdSIsICJnbXVfcGRjIjsKKworCQlpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMzA0IElS UV9UWVBFX0xFVkVMX0hJR0g+LAorCQkJICAgICA8R0lDX1NQSSAzMDUgSVJRX1RZUEVfTEVWRUxf SElHSD47CisJCWludGVycnVwdC1uYW1lcyA9ICJoZmkiLCAiZ211IjsKKworCQljbG9ja3MgPSA8 JmNsb2NrX2dwdWNjIEdQVV9DQ19DWF9HTVVfQ0xLPiwKKwkJCTwmY2xvY2tfZ3B1Y2MgR1BVX0ND X0NYT19DTEs+LAorCQkJPCZjbG9ja19nY2MgR0NDX0REUlNTX0dQVV9BWElfQ0xLPiwKKwkJCTwm Y2xvY2tfZ2NjIEdDQ19HUFVfTUVNTk9DX0dGWF9DTEs+OworCQljbG9jay1uYW1lcyA9ICJnbXUi LCAiY3hvIiwgImF4aSIsICJtZW1ub2MiOworCisJCXBvd2VyLWRvbWFpbnMgPSA8JmNsb2NrX2dw dWNjIEdQVV9DWF9HRFNDPjsKKwkJaW9tbXVzID0gPCZhZHJlbm9fc21tdSA1PjsKKworCQlvcGVy YXRpbmctcG9pbnRzLXYyID0gPCZnbXVfb3BwX3RhYmxlPjsKKwl9OwogfTsKLS0gCjIuMTYuMQoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: jcrouse@codeaurora.org (Jordan Crouse) Date: Fri, 16 Mar 2018 12:51:52 -0600 Subject: [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes In-Reply-To: <20180316185152.32020-1-jcrouse@codeaurora.org> References: <20180316185152.32020-1-jcrouse@codeaurora.org> Message-ID: <20180316185152.32020-3-jcrouse@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 119 +++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 16b5f356ec96..854da6604417 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -312,4 +312,123 @@ }; }; }; + + adreno_smmu: arm,smmu-adreno at 5040000 { + compatible = "qcom,msm8996-smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + }; + + gpu_opp_table: adreno-opp-table { + compatible = "operating-points-v2"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = <416>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = <384>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = <320>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = <256>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = <192>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = <128>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = <64>; + }; + }; + + gpu at 5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + /* + * Look ma, no clocks! The GPU clocks and power are controlled + * entirely by the GMU + */ + + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + gmu = <&gmu>; + }; + + gmu_opp_table: adreno-gmu-opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = <128>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = <48>; + }; + }; + + gmu: gmu at 506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; }; -- 2.16.1