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From: David Weinehall <david.weinehall@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Show dmc debug registers on CFL and GLK
Date: Mon, 19 Mar 2018 15:25:09 +0200	[thread overview]
Message-ID: <20180319132509.GA13928@boom> (raw)
In-Reply-To: <20180316004200.GT3945@intel.com>

On Thu, Mar 15, 2018 at 05:42:00PM -0700, Rodrigo Vivi wrote:
> On Thu, Mar 15, 2018 at 03:35:02PM +0200, David Weinehall wrote:
> > Since Coffee Lake uses the Kaby Lake DMC it's a safe
> > bet that the debug registers are the same. I haven't
> > double-checked that the GLK DMC uses the same registers
> > as BXT, but it seems as good of a guess as any.
> 
> It would be good to check. Last time that I checked we were getting
> deep PC residencies but these registers were zeroed on CFL.
> 
> Also this bit confuses many people since it is not a
> proper residency counter :/

I'll run some tests on all platforms that are supposed to be supported
by this, and compare the behaviour.

> 
> > 
> > Signed-off-by: David Weinehall <david.weinehall@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index c4cc8fef11a0..dad0776d58b4 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2813,13 +2813,14 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> >  		   CSR_VERSION_MINOR(csr->version));
> >  
> > -	if (IS_KABYLAKE(dev_priv) ||
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> >  	    (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> >  		seq_printf(m, "DC3 -> DC5 count: %d\n",
> >  			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
> >  		seq_printf(m, "DC5 -> DC6 count: %d\n",
> >  			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
> > -	} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
> > +	} else if (IS_GEMINILAKE(dev_priv) ||
> > +	           IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
> >  		seq_printf(m, "DC3 -> DC5 count: %d\n",
> >  			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
> >  	}
> > -- 
> > 2.16.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-03-19 13:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-15 13:35 [PATCH] drm/i915: Show dmc debug registers on CFL and GLK David Weinehall
2018-03-15 13:44 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-03-15 13:56 ` [PATCH] " David Weinehall
2018-03-15 14:23 ` ✓ Fi.CI.BAT: success for drm/i915: Show dmc debug registers on CFL and GLK (rev2) Patchwork
2018-03-15 17:13 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-16  0:42 ` [PATCH] drm/i915: Show dmc debug registers on CFL and GLK Rodrigo Vivi
2018-03-19 13:25   ` David Weinehall [this message]
2018-03-18  1:05 ` kbuild test robot
2018-03-18  1:14 ` kbuild test robot

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