From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed Date: Thu, 22 Mar 2018 16:20:27 -0700 Message-ID: <20180322232027.GO2557@intel.com> References: <20180322214848.28022-1-jose.souza@intel.com> <20180322214848.28022-9-jose.souza@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94A026E233 for ; Thu, 22 Mar 2018 23:20:29 +0000 (UTC) Content-Disposition: inline In-Reply-To: <20180322214848.28022-9-jose.souza@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?iso-8859-1?Q?Jos=E9?= Roberto de Souza Cc: intel-gfx@lists.freedesktop.org, Dhinakaran Pandiyan List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCBNYXIgMjIsIDIwMTggYXQgMDI6NDg6NDVQTSAtMDcwMCwgSm9zw6kgUm9iZXJ0byBk ZSBTb3V6YSB3cm90ZToKPiBJbiB0aGUgMiBlRFAxLjRhIHBhbm5lbHMgdGVzdGVkIHNldCBvciBu b3Qgc2V0IGJpdCBoYXZlIG5vIGVmZmVjdAo+IGJ1dCBpcyBiZXR0ZXIgc2V0IGl0IGFuZCBjb21w bHkgd2l0aCBzcGVjaWZpY2F0aW9uLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEpvc8OpIFJvYmVydG8g ZGUgU291emEgPGpvc2Uuc291emFAaW50ZWwuY29tPgo+IENjOiBEaGluYWthcmFuIFBhbmRpeWFu IDxkaGluYWthcmFuLnBhbmRpeWFuQGludGVsLmNvbT4KPiBDYzogUm9kcmlnbyBWaXZpIDxyb2Ry aWdvLnZpdmlAaW50ZWwuY29tPgoKbG9va2luZyBhdCB0aGUgc3BlYyBpdCBzZWVtcyB0aGF0IHdl IG5ldmVyICpyZWFsbHkqIGhhZCBlbmFibGVkIFBTUjIhID18CgpSZXZpZXdlZC1ieTogUm9kcmln byBWaXZpIDxyb2RyaWdvLnZpdmlAaW50ZWwuY29tPgoKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfcHNyLmMgfCAxMiArKysrKystLS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDYg aW5zZXJ0aW9ucygrKSwgNiBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfcHNyLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3Iu Ywo+IGluZGV4IDE5ZWU2MTIwZDNjZC4uZjVjM2JjYWZkZTI1IDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3Bzci5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfcHNyLmMKPiBAQCAtMjc4LDE5ICsyNzgsMTkgQEAgc3RhdGljIHZvaWQgaHN3X3Bzcl9l bmFibGVfc2luayhzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwKQo+ICAJc3RydWN0IGludGVsX2Rp Z2l0YWxfcG9ydCAqZGlnX3BvcnQgPSBkcF90b19kaWdfcG9ydChpbnRlbF9kcCk7Cj4gIAlzdHJ1 Y3QgZHJtX2RldmljZSAqZGV2ID0gZGlnX3BvcnQtPmJhc2UuYmFzZS5kZXY7Cj4gIAlzdHJ1Y3Qg ZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYgPSB0b19pOTE1KGRldik7Cj4gLQo+ICsJdTggZHBj ZF92YWwgPSBEUF9QU1JfRU5BQkxFOwo+ICAKPiAgCS8qIEVuYWJsZSBBTFBNIGF0IHNpbmsgZm9y IHBzcjIgKi8KPiAgCWlmIChkZXZfcHJpdi0+cHNyLnBzcjJfZW5hYmxlZCAmJiBkZXZfcHJpdi0+ cHNyLmFscG0pCj4gIAkJZHJtX2RwX2RwY2Rfd3JpdGViKCZpbnRlbF9kcC0+YXV4LAo+ICAJCQkJ RFBfUkVDRUlWRVJfQUxQTV9DT05GSUcsCj4gIAkJCQlEUF9BTFBNX0VOQUJMRSk7Cj4gKwo+ICsJ aWYgKGRldl9wcml2LT5wc3IucHNyMl9lbmFibGVkKQo+ICsJCWRwY2RfdmFsIHw9IERQX1BTUl9F TkFCTEVfUFNSMjsKPiAgCWlmIChkZXZfcHJpdi0+cHNyLmxpbmtfc3RhbmRieSkKPiAtCQlkcm1f ZHBfZHBjZF93cml0ZWIoJmludGVsX2RwLT5hdXgsIERQX1BTUl9FTl9DRkcsCj4gLQkJCQkgICBE UF9QU1JfRU5BQkxFIHwgRFBfUFNSX01BSU5fTElOS19BQ1RJVkUpOwo+IC0JZWxzZQo+IC0JCWRy bV9kcF9kcGNkX3dyaXRlYigmaW50ZWxfZHAtPmF1eCwgRFBfUFNSX0VOX0NGRywKPiAtCQkJCSAg IERQX1BTUl9FTkFCTEUpOwo+ICsJCWRwY2RfdmFsIHw9IERQX1BTUl9NQUlOX0xJTktfQUNUSVZF Owo+ICsJZHJtX2RwX2RwY2Rfd3JpdGViKCZpbnRlbF9kcC0+YXV4LCBEUF9QU1JfRU5fQ0ZHLCBk cGNkX3ZhbCk7Cj4gIAo+ICAJZHJtX2RwX2RwY2Rfd3JpdGViKCZpbnRlbF9kcC0+YXV4LCBEUF9T RVRfUE9XRVIsIERQX1NFVF9QT1dFUl9EMCk7Cj4gIH0KPiAtLSAKPiAyLjE2LjIKPiAKPiBfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+IEludGVsLWdmeCBt YWlsaW5nIGxpc3QKPiBJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcg bGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==