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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Cc: <cyrille.pitchen@wedev4u.fr>, <marek.vasut@gmail.com>,
	<dwmw2@infradead.org>, <computersforpeace@gmail.com>,
	<boris.brezillon@free-electrons.com>,
	Naga Sureshkumar Relli <nagasure@xilinx.com>,
	linux-mtd@lists.infradead.org
Subject: Re: [RFC PATCH 5/5] devicetree: Add devicetree bindings documentation for
Date: Fri, 23 Mar 2018 15:47:27 +0100	[thread overview]
Message-ID: <20180323154727.6c7951c6@xps13> (raw)
In-Reply-To: <1521807722-21626-6-git-send-email-nagasure@xilinx.com>

Hi Naga,

On Fri, 23 Mar 2018 17:52:02 +0530, Naga Sureshkumar Relli
<naga.sureshkumar.relli@xilinx.com> wrote:

> Add bindings documentation for Zynq QSPI driver.
> 
> Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
> ---
>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> new file mode 100644
> index 0000000..fe3b8e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> @@ -0,0 +1,28 @@
> +Xilinx Zynq QSPI controller Device Tree Bindings
> +-------------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynq-qspi-1.0".

What is this trailing "-1.0" for?

> +- reg			: Physical base address and size of QSPI registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.
> +- interrupt-parent	: Must be core interrupt controller
> +- clock-names		: List of input clock names - "ref_clk", "pclk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +
> +Optional properties:
> +- num-cs		: Number of chip selects used.
> +- is-dual		: QSPI operating in Dual parallel.
> +- is-satcked		: QSPI operating in Stacked mode.

        ^ stacked

BTW, if you have both is-dual and is-stacked properties in the DT, do
you really need a configuration option for that?

> +
> +Example:
> +	qspi@e000d000 {
> +		compatible = "xlnx,zynq-qspi-1.0";
> +		clock-names = "ref_clk", "pclk";
> +		clocks = <&clkc 10>, <&clkc 43>;
> +		interrupt-parent = <&intc>;
> +		interrupts = <0 19 4>;
> +		num-cs = <1>;
> +		reg = <0xe000d000 0x1000>;
> +	} ;

Thanks,
Miquèl

-- 
Miquel Raynal, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

  reply	other threads:[~2018-03-23 14:47 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-23 12:21 [RFC PATCH 0/5] RFC for Zynq QSPI Naga Sureshkumar Relli
2018-03-23 12:21 ` [RFC PATCH 1/5] spi: Add support for Zynq qspi controller Naga Sureshkumar Relli
2018-03-23 12:21 ` [RFC PATCH 2/5] mtd: spi-nor: Add support for Zynq QSPI controller Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 3/5] mtd: spi-nor: Add Dual Parallel and Stacked support for Zynq QSPI Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 4/5] spi: Add PM Support for Zynq QSPI controller Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 5/5] devicetree: Add devicetree bindings documentation for Naga Sureshkumar Relli
2018-03-23 14:47   ` Miquel Raynal [this message]
2018-03-23 12:52 ` [RFC PATCH 0/5] RFC for Zynq QSPI Marek Vasut
2018-03-23 13:39   ` Naga Sureshkumar Relli
2018-04-16  7:25 ` Naga Sureshkumar Relli
     [not found]   ` <CALgLF9K=rZxVx_QXvV_LH3OhidTcguZ=K=p=Lf9AfFbk4H+8Zw@mail.gmail.com>
2018-09-17 15:05     ` Boris Brezillon
2018-09-17 15:07       ` Boris Brezillon
     [not found]       ` <CALgLF9JVweEcEm6L33HaHp4HtXhmsZL7J5FDe8+O11i0Q1nukg@mail.gmail.com>
2018-09-18  7:17         ` Boris Brezillon
2018-09-18  8:58           ` Naga Sureshkumar Relli
2019-06-26  9:53           ` naga suresh kumar
2019-06-26  9:53             ` naga suresh kumar

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