From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Vidya Srinivas <vidya.srinivas@intel.com>
Cc: intel-gfx@lists.freedesktop.org, maarten.lankhorst@intel.com
Subject: Re: [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12
Date: Thu, 29 Mar 2018 12:25:32 +0300 [thread overview]
Message-ID: <20180329092532.GR5453@intel.com> (raw)
In-Reply-To: <1522310762-5055-19-git-send-email-vidya.srinivas@intel.com>
On Thu, Mar 29, 2018 at 01:36:02PM +0530, Vidya Srinivas wrote:
> As per display WA 1106, to avoid corruption issues
> NV12 plane height needs to be multiplier of 4
> Hence we modify the fb src and destination height
> and width to be multiples of 4. Without this, pipe
> fifo underruns were seen on APL and KBL.
>
> Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9c58da0..a1f718d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -159,6 +159,8 @@
> #define INTEL_I2C_BUS_DVO 1
> #define INTEL_I2C_BUS_SDVO 2
>
> +#define MULT4(x) ((x + 3) & ~0x03)
> +
> /* these are outputs from the chip - integrated only
> external chips are via DVO or SDVO output */
> enum intel_output_type {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 538d938..9f466c6 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> crtc_w--;
> crtc_h--;
>
> + if (fb->format->format == DRM_FORMAT_NV12) {
> + src_w = MULT4(src_w);
> + src_h = MULT4(src_h);
> + crtc_w = MULT4(crtc_w);
> + crtc_h = MULT4(crtc_h);
No macros like this pls. I want to know what it's doing. Also this is
wrong. You can't increase src_w/h without potentially pushing the scale
factor past the hardware limits.
> + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w, crtc_h);
No user triggrable errors. Also this doesn't even explain what it's
printing.
> + }
> +
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-03-29 9:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-29 8:05 [PATCH v18 00/18] Add NV12 support Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 01/18] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 02/18] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 03/18] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 04/18] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 05/18] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 06/18] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 07/18] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 08/18] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 09/18] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 10/18] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 11/18] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 12/18] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 13/18] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 14/18] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-03-29 8:05 ` [PATCH v18 15/18] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-03-29 8:06 ` [PATCH v18 16/18] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-03-29 8:06 ` [PATCH v18 17/18] drm/i915: Display WA 827 Vidya Srinivas
2018-03-29 8:06 ` [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12 Vidya Srinivas
2018-03-29 8:48 ` Maarten Lankhorst
2018-03-29 9:19 ` Srinivas, Vidya
2018-03-29 10:28 ` Maarten Lankhorst
2018-03-29 10:31 ` Srinivas, Vidya
2018-03-29 11:33 ` Ville Syrjälä
2018-04-02 9:17 ` Srinivas, Vidya
2018-04-02 9:55 ` Srinivas, Vidya
2018-03-29 9:25 ` Ville Syrjälä [this message]
2018-03-29 9:29 ` Srinivas, Vidya
2018-03-29 9:33 ` Ville Syrjälä
2018-03-29 9:39 ` Srinivas, Vidya
2018-03-29 8:47 ` ✓ Fi.CI.BAT: success for Add NV12 support (rev6) Patchwork
2018-03-29 12:17 ` ✗ Fi.CI.IGT: failure " Patchwork
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