From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed Date: Fri, 30 Mar 2018 10:41:08 -0700 Message-ID: <20180330174108.GH2338@intel.com> References: <20180328223046.16125-1-jose.souza@intel.com> <20180328223046.16125-9-jose.souza@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20180328223046.16125-9-jose.souza@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?iso-8859-1?Q?Jos=E9?= Roberto de Souza Cc: intel-gfx@lists.freedesktop.org, Dhinakaran Pandiyan , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gV2VkLCBNYXIgMjgsIDIwMTggYXQgMDM6MzA6NDVQTSAtMDcwMCwgSm9zw6kgUm9iZXJ0byBk ZSBTb3V6YSB3cm90ZToKPiBJbiB0aGUgMiBlRFAxLjRhIHBhbm5lbHMgdGVzdGVkIHNldCBvciBu b3Qgc2V0IGJpdCBoYXZlIG5vIGVmZmVjdAo+IGJ1dCBpcyBiZXR0ZXIgc2V0IGl0IGFuZCBjb21w bHkgd2l0aCBzcGVjaWZpY2F0aW9uLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEpvc8OpIFJvYmVydG8g ZGUgU291emEgPGpvc2Uuc291emFAaW50ZWwuY29tPgo+IENjOiBEaGluYWthcmFuIFBhbmRpeWFu IDxkaGluYWthcmFuLnBhbmRpeWFuQGludGVsLmNvbT4KPiBSZXZpZXdlZC1ieTogUm9kcmlnbyBW aXZpIDxyb2RyaWdvLnZpdmlAaW50ZWwuY29tPgoKcGF0Y2hlcyAxLTkgcHVzaGVkIHRvIGRpbnEu IFRoYW5rcyBmb3IgcGF0Y2hlcyBhbmQgcmV2aWV3cy4KCj4gLS0tCj4gCj4gdjM6IHJlYmFzZWQK PiAKPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcHNyLmMgfCAxMSArKysrKystLS0tLQo+ ICAxIGZpbGUgY2hhbmdlZCwgNiBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+IAo+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYyBiL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2ludGVsX3Bzci5jCj4gaW5kZXggZDA3OWNmMGIwMzRjLi4yZDUzZjczOThhNmQg MTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcHNyLmMKPiArKysgYi9k cml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYwo+IEBAIC0yNzgsMTggKzI3OCwxOSBAQCBz dGF0aWMgdm9pZCBoc3dfcHNyX2VuYWJsZV9zaW5rKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAp Cj4gIAlzdHJ1Y3QgaW50ZWxfZGlnaXRhbF9wb3J0ICpkaWdfcG9ydCA9IGRwX3RvX2RpZ19wb3J0 KGludGVsX2RwKTsKPiAgCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBkaWdfcG9ydC0+YmFzZS5i YXNlLmRldjsKPiAgCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUo ZGV2KTsKPiArCXU4IGRwY2RfdmFsID0gRFBfUFNSX0VOQUJMRTsKPiAgCj4gIAkvKiBFbmFibGUg QUxQTSBhdCBzaW5rIGZvciBwc3IyICovCj4gIAlpZiAoZGV2X3ByaXYtPnBzci5wc3IyX2VuYWJs ZWQgJiYgZGV2X3ByaXYtPnBzci5hbHBtKQo+ICAJCWRybV9kcF9kcGNkX3dyaXRlYigmaW50ZWxf ZHAtPmF1eCwKPiAgCQkJCURQX1JFQ0VJVkVSX0FMUE1fQ09ORklHLAo+ICAJCQkJRFBfQUxQTV9F TkFCTEUpOwo+ICsKPiArCWlmIChkZXZfcHJpdi0+cHNyLnBzcjJfZW5hYmxlZCkKPiArCQlkcGNk X3ZhbCB8PSBEUF9QU1JfRU5BQkxFX1BTUjI7Cj4gIAlpZiAoZGV2X3ByaXYtPnBzci5saW5rX3N0 YW5kYnkpCj4gLQkJZHJtX2RwX2RwY2Rfd3JpdGViKCZpbnRlbF9kcC0+YXV4LCBEUF9QU1JfRU5f Q0ZHLAo+IC0JCQkJICAgRFBfUFNSX0VOQUJMRSB8IERQX1BTUl9NQUlOX0xJTktfQUNUSVZFKTsK PiAtCWVsc2UKPiAtCQlkcm1fZHBfZHBjZF93cml0ZWIoJmludGVsX2RwLT5hdXgsIERQX1BTUl9F Tl9DRkcsCj4gLQkJCQkgICBEUF9QU1JfRU5BQkxFKTsKPiArCQlkcGNkX3ZhbCB8PSBEUF9QU1Jf TUFJTl9MSU5LX0FDVElWRTsKPiArCWRybV9kcF9kcGNkX3dyaXRlYigmaW50ZWxfZHAtPmF1eCwg RFBfUFNSX0VOX0NGRywgZHBjZF92YWwpOwo+ICAKPiAgCWRybV9kcF9kcGNkX3dyaXRlYigmaW50 ZWxfZHAtPmF1eCwgRFBfU0VUX1BPV0VSLCBEUF9TRVRfUE9XRVJfRDApOwo+ICB9Cj4gLS0gCj4g Mi4xNi4zCj4gCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KPiBJbnRlbC1nZnggbWFpbGluZyBsaXN0Cj4gSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCklu dGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRw czovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=