From: aurelien@aurel32.net (Aurelien Jarno)
To: linux-riscv@lists.infradead.org
Subject: [RFC PR] RISC-V changes for 4.17
Date: Wed, 4 Apr 2018 00:06:55 +0200 [thread overview]
Message-ID: <20180403220655.GA8917@aurel32.net> (raw)
In-Reply-To: <mhng-2eb61f09-8a89-482b-995b-5ae38b73dfe9@palmer-si-x1c4>
Hi Palmer,
On 2018-04-02 20:58, Palmer Dabbelt wrote:
> Here's the PR I'm planning on submitting to Linus for the first half of the
> 4.17 merge window. Unless anyone knows of any problems I'll submit the PR on
> Wednesday morning. I haven't given this a much testing as I probably should
> have, so please go give things a shot!
> I don't want to take any new code for Wednesday, but I'm planning on taking the
> perf stuff for next week if some small issues iron themselves out.
Do you think it's possible to also include this simple change:
http://lists.infradead.org/pipermail/linux-riscv/2018-March/000292.html
It fixes building the kernel with compilers defaulting to PIE and is a
no-op for compilers not defaulting to PIE.
Thanks,
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien at aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2018-04-03 22:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-03 3:58 [RFC PR] RISC-V changes for 4.17 Palmer Dabbelt
2018-04-03 22:06 ` Aurelien Jarno [this message]
2018-04-04 0:27 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2018-04-03 7:22 Atish Patra
2018-04-03 18:34 ` Palmer Dabbelt
2018-04-03 22:39 ` Atish Patra
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